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[PULL 1/6] target/arm: Fix MTE access checks for disabled SEL2
From: |
Peter Maydell |
Subject: |
[PULL 1/6] target/arm: Fix MTE access checks for disabled SEL2 |
Date: |
Fri, 1 Apr 2022 16:00:50 +0100 |
From: Idan Horowitz <idan.horowitz@gmail.com>
While not mentioned anywhere in the actual specification text, the
HCR_EL2.ATA bit is treated as '1' when EL2 is disabled at the current
security state. This can be observed in the psuedo-code implementation
of AArch64.AllocationTagAccessIsEnabled().
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220328173107.311267-1-idan.horowitz@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 2 +-
target/arm/helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a34be2e4595..7f696cd36a8 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1094,7 +1094,7 @@ static inline bool
allocation_tag_access_enabled(CPUARMState *env, int el,
&& !(env->cp15.scr_el3 & SCR_ATA)) {
return false;
}
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
+ if (el < 2 && arm_is_el2_enabled(env)) {
uint64_t hcr = arm_hcr_el2_eff(env);
if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
return false;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 812ca591f4e..3aeaea40683 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7176,7 +7176,7 @@ static CPAccessResult access_mte(CPUARMState *env, const
ARMCPRegInfo *ri,
{
int el = arm_current_el(env);
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
+ if (el < 2 && arm_is_el2_enabled(env)) {
uint64_t hcr = arm_hcr_el2_eff(env);
if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
return CP_ACCESS_TRAP_EL2;
--
2.25.1
- [PULL 0/6] target-arm queue, Peter Maydell, 2022/04/01
- [PULL 3/6] target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk, Peter Maydell, 2022/04/01
- [PULL 5/6] MAINTAINERS: change Fred Konrad's email address, Peter Maydell, 2022/04/01
- [PULL 4/6] target/arm: Determine final stage 2 output PA space based on original IPA, Peter Maydell, 2022/04/01
- [PULL 1/6] target/arm: Fix MTE access checks for disabled SEL2,
Peter Maydell <=
- [PULL 6/6] target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen, Peter Maydell, 2022/04/01
- [PULL 2/6] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space, Peter Maydell, 2022/04/01
- Re: [PULL 0/6] target-arm queue, Peter Maydell, 2022/04/02