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From: | yangxiaojuan |
Subject: | Re: [PATCH v1 33/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) |
Date: | Thu, 21 Apr 2022 11:10:32 +0800 |
User-agent: | Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 |
Sorry, I didn't understand your means before.
The emulate of PCH_PIC_CLR in qemu LoongArchPCHPIC struct member is intirr_lo/hi(we devide 64bits reg to two 32bits reg to match the linux kernel), it will be changed when we config clear reg or handler irq.
static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
...
case PCH_PIC_INT_CLEAR_LO:
if (s->intedge_lo & data) {
s->intirr_lo &= (~data);
pch_pic_update_irq(s, data, 0, 0);
s->intisr_lo &= (~data);
}
break;
case PCH_PIC_INT_CLEAR_HI:
if (s->intedge_hi & data) {
s->intirr_hi &= (~data);
pch_pic_update_irq(s, data, 0, 1);
s->intisr_hi &= (~data);
}
break;
One can just as easily do
case PCH_PIC_INT_CLEAR_LO:
data = ""
goto do_clear;
case PCH_PIC_INT_CLEAR_HI:
data <<= 32;
do_clear:
s->intrr &= ~data;
pch_pic_update_irq(s...);
s->intrs &= ~data;
with the values internal to qemu be represented with uint64_t instead of a pair of uint32_t. Which would in fact be *much* clearer to read, and would seem to cut down the number of code lines required by half.
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