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[PULL 08/31] target/riscv: Enable privileged spec version 1.12
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From: |
Alistair Francis |
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Subject: |
[PULL 08/31] target/riscv: Enable privileged spec version 1.12 |
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Date: |
Thu, 21 Apr 2022 16:36:07 +1000 |
From: Atish Patra <atishp@rivosinc.com>
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 8 +++++---
target/riscv/csr.c | 5 +++++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..c3fd018ecb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
- set_priv_version(env, PRIV_VERSION_1_11_0);
+ set_priv_version(env, PRIV_VERSION_1_12_0);
}
#if defined(TARGET_RISCV64)
@@ -503,7 +503,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (cpu->cfg.priv_spec) {
- if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+ priv_version = PRIV_VERSION_1_12_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
priv_version = PRIV_VERSION_1_11_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
priv_version = PRIV_VERSION_1_10_0;
@@ -518,7 +520,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
if (priv_version) {
set_priv_version(env, priv_version);
} else if (!env->priv_ver) {
- set_priv_version(env, PRIV_VERSION_1_11_0);
+ set_priv_version(env, PRIV_VERSION_1_12_0);
}
if (cpu->cfg.mmu) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 84a398b205..8b6a1b90f1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2975,6 +2975,7 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
int read_only = get_field(csrno, 0xC00) == 3;
+ int csr_min_priv = csr_ops[csrno].min_priv_ver;
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
@@ -3007,6 +3008,10 @@ static inline RISCVException
riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv_ver < csr_min_priv) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
return csr_ops[csrno].predicate(env, csrno);
}
--
2.35.1
- [PULL 00/31] riscv-to-apply queue, Alistair Francis, 2022/04/21
- [PULL 01/31] hw/ssi: Add Ibex SPI device model, Alistair Francis, 2022/04/21
- [PULL 02/31] riscv: opentitan: Connect opentitan SPI Host, Alistair Francis, 2022/04/21
- [PULL 03/31] target/riscv: Define simpler privileged spec version numbering, Alistair Francis, 2022/04/21
- [PULL 04/31] target/riscv: Add the privileged spec version 1.12.0, Alistair Francis, 2022/04/21
- [PULL 05/31] target/riscv: Introduce privilege version field in the CSR ops., Alistair Francis, 2022/04/21
- [PULL 06/31] target/riscv: Add support for mconfigptr, Alistair Francis, 2022/04/21
- [PULL 07/31] target/riscv: Add *envcfg* CSRs support, Alistair Francis, 2022/04/21
- [PULL 08/31] target/riscv: Enable privileged spec version 1.12,
Alistair Francis <=
- [PULL 09/31] target/riscv: cpu: Fixup indentation, Alistair Francis, 2022/04/21
- [PULL 10/31] target/riscv: Allow software access to MIP SEIP, Alistair Francis, 2022/04/21
- [PULL 12/31] target/riscv: optimize condition assign for scale < 0, Alistair Francis, 2022/04/21
- [PULL 14/31] target/riscv: misa to ISA string conversion fix, Alistair Francis, 2022/04/21
- [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension, Alistair Francis, 2022/04/21
- [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v, Alistair Francis, 2022/04/21
- [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21
- [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults, Alistair Francis, 2022/04/21
- [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21