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[PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu f
From: |
Alistair Francis |
Subject: |
[PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults |
Date: |
Thu, 21 Apr 2022 16:36:16 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
The riscv_raise_exception function stores its argument into
exception_index and then exits to the main loop. When we
have already set exception_index, we can just exit directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1c60fb2e80..126251d5da 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1150,7 +1150,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
env->badaddr = addr;
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(mmu_idx);
- riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
+ cpu_loop_exit_restore(cs, retaddr);
}
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
@@ -1175,7 +1175,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
env->badaddr = addr;
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(mmu_idx);
- riscv_raise_exception(env, cs->exception_index, retaddr);
+ cpu_loop_exit_restore(cs, retaddr);
}
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -1311,7 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
first_stage_error,
riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(mmu_idx));
- riscv_raise_exception(env, cs->exception_index, retaddr);
+ cpu_loop_exit_restore(cs, retaddr);
}
return true;
--
2.35.1
- [PULL 07/31] target/riscv: Add *envcfg* CSRs support, (continued)
- [PULL 07/31] target/riscv: Add *envcfg* CSRs support, Alistair Francis, 2022/04/21
- [PULL 08/31] target/riscv: Enable privileged spec version 1.12, Alistair Francis, 2022/04/21
- [PULL 09/31] target/riscv: cpu: Fixup indentation, Alistair Francis, 2022/04/21
- [PULL 10/31] target/riscv: Allow software access to MIP SEIP, Alistair Francis, 2022/04/21
- [PULL 12/31] target/riscv: optimize condition assign for scale < 0, Alistair Francis, 2022/04/21
- [PULL 14/31] target/riscv: misa to ISA string conversion fix, Alistair Francis, 2022/04/21
- [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension, Alistair Francis, 2022/04/21
- [PULL 13/31] target/riscv: optimize helper for vmv<nr>r.v, Alistair Francis, 2022/04/21
- [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21
- [PULL 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults,
Alistair Francis <=
- [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21
- [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow, Alistair Francis, 2022/04/21
- [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled, Alistair Francis, 2022/04/21
- [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable, Alistair Francis, 2022/04/21
- [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices, Alistair Francis, 2022/04/21
- [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 2022/04/21
- [PULL 26/31] target/riscv: cpu: Add a config option for native debug, Alistair Francis, 2022/04/21
- [PULL 27/31] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 2022/04/21