[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 04/31] hw/arm: versal: Create an APU CPU Cluster
From: |
Peter Maydell |
Subject: |
[PULL 04/31] hw/arm: versal: Create an APU CPU Cluster |
Date: |
Thu, 21 Apr 2022 12:18:19 +0100 |
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
Create an APU CPU Cluster. This is in preparation to add the RPU.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-versal.h | 2 ++
hw/arm/xlnx-versal.c | 9 ++++++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 0728316ec77..d2d3028e185 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -14,6 +14,7 @@
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
+#include "hw/cpu/cluster.h"
#include "hw/or-irq.h"
#include "hw/sd/sdhci.h"
#include "hw/intc/arm_gicv3.h"
@@ -49,6 +50,7 @@ struct Versal {
struct {
struct {
MemoryRegion mr;
+ CPUClusterState cluster;
ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
GICv3State gic;
} apu;
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 2551dfc22d6..4415ee413fc 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -34,10 +34,15 @@ static void versal_create_apu_cpus(Versal *s)
{
int i;
+ object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
+ TYPE_CPU_CLUSTER);
+ qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
+
for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
Object *obj;
- object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
+ object_initialize_child(OBJECT(&s->fpd.apu.cluster),
+ "apu-cpu[*]", &s->fpd.apu.cpu[i],
XLNX_VERSAL_ACPU_TYPE);
obj = OBJECT(&s->fpd.apu.cpu[i]);
if (i) {
@@ -52,6 +57,8 @@ static void versal_create_apu_cpus(Versal *s)
&error_abort);
qdev_realize(DEVICE(obj), NULL, &error_fatal);
}
+
+ qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
}
static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
--
2.25.1
- [PULL 00/31] target-arm queue, Peter Maydell, 2022/04/21
- [PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF, Peter Maydell, 2022/04/21
- [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers, Peter Maydell, 2022/04/21
- [PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding, Peter Maydell, 2022/04/21
- [PULL 04/31] hw/arm: versal: Create an APU CPU Cluster,
Peter Maydell <=
- [PULL 07/31] hw/arm: versal: Connect the CRL, Peter Maydell, 2022/04/21
- [PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL, Peter Maydell, 2022/04/21
- [PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs, Peter Maydell, 2022/04/21
- [PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device, Peter Maydell, 2022/04/21
- [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct, Peter Maydell, 2022/04/21
- [PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE, Peter Maydell, 2022/04/21
- [PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct, Peter Maydell, 2022/04/21
- [PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs, Peter Maydell, 2022/04/21
- [PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table, Peter Maydell, 2022/04/21
- [PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners, Peter Maydell, 2022/04/21