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[PULL 5/7] hw/rx: rx-gdbsim DTB load address aligned of 16byte.
From: |
Richard Henderson |
Subject: |
[PULL 5/7] hw/rx: rx-gdbsim DTB load address aligned of 16byte. |
Date: |
Thu, 21 Apr 2022 10:31:12 -0700 |
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Linux kernel required alined address of DTB.
But missing align in dtb load function.
Fixed to load to the correct address.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220207132758.84403-1-ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/rx/rx-gdbsim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c
index 64f897e5b1..be147b4bd9 100644
--- a/hw/rx/rx-gdbsim.c
+++ b/hw/rx/rx-gdbsim.c
@@ -141,7 +141,7 @@ static void rx_gdbsim_init(MachineState *machine)
exit(1);
}
/* DTB is located at the end of SDRAM space. */
- dtb_offset = machine->ram_size - dtb_size;
+ dtb_offset = ROUND_DOWN(machine->ram_size - dtb_size, 16);
rom_add_blob_fixed("dtb", dtb, dtb_size,
SDRAM_BASE + dtb_offset);
/* Set dtb address to R1 */
--
2.34.1
- [PULL 0/7] target/rx patch queue, Richard Henderson, 2022/04/21
- [PULL 1/7] target/rx: Put tb_flags into DisasContext, Richard Henderson, 2022/04/21
- [PULL 3/7] target/rx: Move DISAS_UPDATE check for write to PSW, Richard Henderson, 2022/04/21
- [PULL 4/7] target/rx: Swap stack pointers on clrpsw/setpsw instruction, Richard Henderson, 2022/04/21
- [PULL 2/7] target/rx: Store PSW.U in tb->flags, Richard Henderson, 2022/04/21
- [PULL 5/7] hw/rx: rx-gdbsim DTB load address aligned of 16byte.,
Richard Henderson <=
- [PULL 6/7] target/rx: set PSW.I when executing wait instruction, Richard Henderson, 2022/04/21
- [PULL 7/7] target/rx: update PC correctly in wait instruction, Richard Henderson, 2022/04/21
- Re: [PULL 0/7] target/rx patch queue, Richard Henderson, 2022/04/21