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[PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes
From: |
Max Filippov |
Subject: |
[PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes |
Date: |
Thu, 21 Apr 2022 14:39:17 -0700 |
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- gen_callw_slot uses callinc (1..3);
- translate_entry passes stack register number (0..15) to the helper;
- gen_check_exclusive passes boolean to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/translate.c | 44 ++++++++++++---------------------------
1 file changed, 13 insertions(+), 31 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index fb4d80669c47..b3f8348dee26 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -406,11 +406,8 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int
slot)
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
- TCGv_i32 tcallinc = tcg_const_i32(callinc);
-
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
- tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
- tcg_temp_free(tcallinc);
+ tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fffffff));
gen_jump_slot(dc, dest, slot);
@@ -456,9 +453,7 @@ static void gen_brcond(DisasContext *dc, TCGCond cond,
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
- TCGv_i32 tmp = tcg_const_i32(t1);
- gen_brcond(dc, cond, t0, tmp, addr);
- tcg_temp_free(tmp);
+ gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
@@ -543,21 +538,6 @@ static MemOp gen_load_store_alignment(DisasContext *dc,
MemOp mop,
return mop;
}
-#ifndef CONFIG_USER_ONLY
-static void gen_waiti(DisasContext *dc, uint32_t imm4)
-{
- TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
- TCGv_i32 intlevel = tcg_const_i32(imm4);
-
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_waiti(cpu_env, pc, intlevel);
- tcg_temp_free(pc);
- tcg_temp_free(intlevel);
-}
-#endif
-
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
@@ -1663,11 +1643,10 @@ static void translate_entry(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 pc = tcg_const_i32(dc->pc);
- TCGv_i32 s = tcg_const_i32(arg[0].imm);
+ TCGv_i32 s = tcg_constant_i32(arg[0].imm);
TCGv_i32 imm = tcg_const_i32(arg[1].imm);
gen_helper_entry(cpu_env, pc, s, imm);
tcg_temp_free(imm);
- tcg_temp_free(s);
tcg_temp_free(pc);
}
@@ -1749,11 +1728,10 @@ static void gen_check_exclusive(DisasContext *dc,
TCGv_i32 addr, bool is_write)
{
if (!option_enabled(dc, XTENSA_OPTION_MPU)) {
TCGv_i32 tpc = tcg_const_i32(dc->pc);
- TCGv_i32 write = tcg_const_i32(is_write);
- gen_helper_check_exclusive(cpu_env, tpc, addr, write);
+ gen_helper_check_exclusive(cpu_env, tpc, addr,
+ tcg_constant_i32(is_write));
tcg_temp_free(tpc);
- tcg_temp_free(write);
}
}
#endif
@@ -2517,9 +2495,7 @@ static void translate_ssa8l(DisasContext *dc, const
OpcodeArg arg[],
static void translate_ssai(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_const_i32(arg[0].imm);
- gen_right_shift_sar(dc, tmp);
- tcg_temp_free(tmp);
+ gen_right_shift_sar(dc, tcg_constant_i32(arg[0].imm));
}
static void translate_ssl(DisasContext *dc, const OpcodeArg arg[],
@@ -2553,7 +2529,13 @@ static void translate_waiti(DisasContext *dc, const
OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_waiti(dc, arg[0].imm);
+ TCGv_i32 pc = tcg_const_i32(dc->base.pc_next);
+
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm));
+ tcg_temp_free(pc);
#endif
}
--
2.30.2
- [PATCH 0/6] target/xtensa: use tcg_constant_* where possible, Max Filippov, 2022/04/21
- [PATCH 1/6] target/xtensa: use tcg_contatnt_* for numeric literals, Max Filippov, 2022/04/21
- [PATCH 2/6] target/xtensa: use tcg_constant_* for exceptions, Max Filippov, 2022/04/21
- [PATCH 3/6] target/xtensa: use tcg_constant_* for TLB opcodes, Max Filippov, 2022/04/21
- [PATCH 6/6] target/xtensa: use tcg_constant_* for remaining opcodes,
Max Filippov <=
- [PATCH 4/6] target/xtensa: use tcg_constant_* for numbered special registers, Max Filippov, 2022/04/21
- [PATCH 5/6] target/xtensa: use tcg_constant_* for FPU conversion opcodes, Max Filippov, 2022/04/21