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[PULL v2 03/31] target/riscv: Define simpler privileged spec version num
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From: |
Alistair Francis |
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Subject: |
[PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering |
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Date: |
Fri, 22 Apr 2022 10:36:28 +1000 |
From: Atish Patra <atishp@rivosinc.com>
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 72f1c9451e..345ec2c773 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -82,8 +82,11 @@ enum {
RISCV_FEATURE_AIA
};
-#define PRIV_VERSION_1_10_0 0x00011000
-#define PRIV_VERSION_1_11_0 0x00011100
+/* Privileged specification version */
+enum {
+ PRIV_VERSION_1_10_0 = 0,
+ PRIV_VERSION_1_11_0,
+};
#define VEXT_VERSION_1_00_0 0x00010000
--
2.35.1
- [PULL v2 00/31] riscv-to-apply queue, Alistair Francis, 2022/04/21
- [PULL v2 01/31] hw/ssi: Add Ibex SPI device model, Alistair Francis, 2022/04/21
- [PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host, Alistair Francis, 2022/04/21
- [PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering,
Alistair Francis <=
- [PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops., Alistair Francis, 2022/04/21
- [PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0, Alistair Francis, 2022/04/21
- [PULL v2 06/31] target/riscv: Add support for mconfigptr, Alistair Francis, 2022/04/21
- [PULL v2 07/31] target/riscv: Add *envcfg* CSRs support, Alistair Francis, 2022/04/21
- [PULL v2 08/31] target/riscv: Enable privileged spec version 1.12, Alistair Francis, 2022/04/21
- [PULL v2 09/31] target/riscv: cpu: Fixup indentation, Alistair Francis, 2022/04/21
- [PULL v2 10/31] target/riscv: Allow software access to MIP SEIP, Alistair Francis, 2022/04/21
- [PULL v2 12/31] target/riscv: optimize condition assign for scale < 0, Alistair Francis, 2022/04/21
- [PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension, Alistair Francis, 2022/04/21
- [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21