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[PULL v2 12/31] target/riscv: optimize condition assign for scale < 0
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From: |
Alistair Francis |
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Subject: |
[PULL v2 12/31] target/riscv: optimize condition assign for scale < 0 |
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Date: |
Fri, 22 Apr 2022 10:36:37 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
for some cases, scale is always equal or less than 0, since lmul is not larger
than 3
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220325085902.29500-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 8d675db9a2..b336d57270 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
static inline uint32_t MAXSZ(DisasContext *s)
{
int scale = s->lmul - 3;
- return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+ return s->cfg_ptr->vlen >> -scale;
}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
*a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
- int vlmax = scale < 0 ?
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+ int vlmax = s->cfg_ptr->vlen >> -scale;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr
*a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
- int vlmax = scale < 0 ?
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+ int vlmax = s->cfg_ptr->vlen >> -scale;
if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
--
2.35.1
- [PULL v2 01/31] hw/ssi: Add Ibex SPI device model, (continued)
- [PULL v2 01/31] hw/ssi: Add Ibex SPI device model, Alistair Francis, 2022/04/21
- [PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host, Alistair Francis, 2022/04/21
- [PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering, Alistair Francis, 2022/04/21
- [PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops., Alistair Francis, 2022/04/21
- [PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0, Alistair Francis, 2022/04/21
- [PULL v2 06/31] target/riscv: Add support for mconfigptr, Alistair Francis, 2022/04/21
- [PULL v2 07/31] target/riscv: Add *envcfg* CSRs support, Alistair Francis, 2022/04/21
- [PULL v2 08/31] target/riscv: Enable privileged spec version 1.12, Alistair Francis, 2022/04/21
- [PULL v2 09/31] target/riscv: cpu: Fixup indentation, Alistair Francis, 2022/04/21
- [PULL v2 10/31] target/riscv: Allow software access to MIP SEIP, Alistair Francis, 2022/04/21
- [PULL v2 12/31] target/riscv: optimize condition assign for scale < 0,
Alistair Francis <=
- [PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension, Alistair Francis, 2022/04/21
- [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21
- [PULL v2 14/31] target/riscv: misa to ISA string conversion fix, Alistair Francis, 2022/04/21
- [PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v, Alistair Francis, 2022/04/21
- [PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults, Alistair Francis, 2022/04/21
- [PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21
- [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow, Alistair Francis, 2022/04/21
- [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21