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[PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devi
From: |
Alistair Francis |
Subject: |
[PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices |
Date: |
Fri, 22 Apr 2022 10:36:49 +1000 |
From: Jim Shu <jim.shu@sifive.com>
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220420080901.14655-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index 3b3ab548f6..0412edc982 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev,
Error **errp)
}
}
+static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
+{
+ /*
+ * According to RISC-V ACLINT spec:
+ * - On MTIMER device reset, the MTIME register is cleared to zero.
+ * - On MTIMER device reset, the MTIMECMP registers are in unknown state.
+ */
+ RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj);
+
+ /*
+ * Clear mtime register by writing to 0 it.
+ * Pending mtime interrupts will also be cleared at the same time.
+ */
+ riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
+}
+
static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_aclint_mtimer_realize;
device_class_set_props(dc, riscv_aclint_mtimer_properties);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ rc->phases.enter = riscv_aclint_mtimer_reset_enter;
}
static const TypeInfo riscv_aclint_mtimer_info = {
@@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev,
Error **errp)
}
}
+static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)
+{
+ /*
+ * According to RISC-V ACLINT spec:
+ * - On MSWI device reset, each MSIP register is cleared to zero.
+ *
+ * p.s. SSWI device reset does nothing since SETSIP register always reads
0.
+ */
+ RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj);
+ int i;
+
+ if (!swi->sswi) {
+ for (i = 0; i < swi->num_harts; i++) {
+ /* Clear MSIP registers by lowering software interrupts. */
+ qemu_irq_lower(swi->soft_irqs[i]);
+ }
+ }
+}
+
static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_aclint_swi_realize;
device_class_set_props(dc, riscv_aclint_swi_properties);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ rc->phases.enter = riscv_aclint_swi_reset_enter;
}
static const TypeInfo riscv_aclint_swi_info = {
--
2.35.1
- [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree, (continued)
- [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree, Alistair Francis, 2022/04/21
- [PULL v2 14/31] target/riscv: misa to ISA string conversion fix, Alistair Francis, 2022/04/21
- [PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v, Alistair Francis, 2022/04/21
- [PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0, Alistair Francis, 2022/04/21
- [PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults, Alistair Francis, 2022/04/21
- [PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM, Alistair Francis, 2022/04/21
- [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow, Alistair Francis, 2022/04/21
- [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT, Alistair Francis, 2022/04/21
- [PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled, Alistair Francis, 2022/04/21
- [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices,
Alistair Francis <=
- [PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps, Alistair Francis, 2022/04/21
- [PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable, Alistair Francis, 2022/04/21
- [PULL v2 26/31] target/riscv: cpu: Add a config option for native debug, Alistair Francis, 2022/04/21
- [PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write, Alistair Francis, 2022/04/21
- [PULL v2 28/31] target/riscv: machine: Add debug state description, Alistair Francis, 2022/04/21
- [PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Alistair Francis, 2022/04/21
- [PULL v2 29/31] target/riscv: cpu: Enable native debug feature, Alistair Francis, 2022/04/21
- [PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address., Alistair Francis, 2022/04/21
- Re: [PULL v2 00/31] riscv-to-apply queue, Richard Henderson, 2022/04/22