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[PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows
From: |
Jonathan Cameron |
Subject: |
[PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows |
Date: |
Fri, 29 Apr 2022 15:41:00 +0100 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
hw/i386/pc.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index b56af1e4e7..dd7cffd340 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -817,7 +817,7 @@ void pc_memory_init(PCMachineState *pcms,
MachineClass *mc = MACHINE_GET_CLASS(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
X86MachineState *x86ms = X86_MACHINE(pcms);
- hwaddr cxl_base;
+ hwaddr cxl_base, cxl_resv_end = 0;
assert(machine->ram_size == x86ms->below_4g_mem_size +
x86ms->above_4g_mem_size);
@@ -925,6 +925,24 @@ void pc_memory_init(PCMachineState *pcms,
e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
memory_region_add_subregion(system_memory, cxl_base, mr);
+ cxl_resv_end = cxl_base + cxl_size;
+ if (machine->cxl_devices_state->fixed_windows) {
+ hwaddr cxl_fmw_base;
+ GList *it;
+
+ cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
+ for (it = machine->cxl_devices_state->fixed_windows; it; it =
it->next) {
+ CXLFixedWindow *fw = it->data;
+
+ fw->base = cxl_fmw_base;
+ memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
+ "cxl-fixed-memory-region", fw->size);
+ memory_region_add_subregion(system_memory, fw->base, &fw->mr);
+ e820_add_entry(fw->base, fw->size, E820_RESERVED);
+ cxl_fmw_base += fw->size;
+ cxl_resv_end = cxl_fmw_base;
+ }
+ }
}
/* Initialize PC system firmware */
@@ -954,6 +972,10 @@ void pc_memory_init(PCMachineState *pcms,
if (!pcmc->broken_reserved_end) {
res_mem_end += memory_region_size(&machine->device_memory->mr);
}
+
+ if (machine->cxl_devices_state->is_enabled) {
+ res_mem_end = cxl_resv_end;
+ }
*val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
}
@@ -990,6 +1012,13 @@ uint64_t pc_pci_hole64_start(void)
if (ms->cxl_devices_state->host_mr.addr) {
hole64_start = ms->cxl_devices_state->host_mr.addr +
memory_region_size(&ms->cxl_devices_state->host_mr);
+ if (ms->cxl_devices_state->fixed_windows) {
+ GList *it;
+ for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next)
{
+ CXLFixedWindow *fw = it->data;
+ hole64_start = fw->mr.addr + memory_region_size(&fw->mr);
+ }
+ }
} else if (pcmc->has_reserved_memory && ms->device_memory->base) {
hole64_start = ms->device_memory->base;
if (!pcmc->broken_reserved_end) {
--
2.32.0
- [PATCH v10 25/45] acpi/cxl: Create the CEDT (9.14.1), (continued)
- [PATCH v10 25/45] acpi/cxl: Create the CEDT (9.14.1), Jonathan Cameron, 2022/04/29
- [PATCH v10 26/45] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Jonathan Cameron, 2022/04/29
- [PATCH v10 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows., Jonathan Cameron, 2022/04/29
- [PATCH v10 28/45] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/04/29
- [PATCH v10 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/04/29
- [PATCH v10 30/45] pci/pcie_port: Add pci_find_port_by_pn(), Jonathan Cameron, 2022/04/29
- [PATCH v10 31/45] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/04/29
- [PATCH v10 32/45] mem/cxl_type3: Add read and write functions for associated hostmem., Jonathan Cameron, 2022/04/29
- [PATCH v10 33/45] cxl/cxl-host: Add memops for CFMWS region., Jonathan Cameron, 2022/04/29
- [PATCH v10 34/45] hw/cxl/component Add a dumb HDM decoder handler, Jonathan Cameron, 2022/04/29
- [PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows,
Jonathan Cameron <=
- [PATCH v10 36/45] tests/acpi: q35: Allow addition of a CXL test., Jonathan Cameron, 2022/04/29
- [PATCH v10 37/45] qtests/bios-tables-test: Add a test for CXL emulation., Jonathan Cameron, 2022/04/29
- [PATCH v10 38/45] tests/acpi: Add tables for CXL emulation., Jonathan Cameron, 2022/04/29
- [PATCH v10 39/45] qtest/cxl: Add more complex test cases with CFMWs, Jonathan Cameron, 2022/04/29
- [PATCH v10 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl, Jonathan Cameron, 2022/04/29
- [PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL, Jonathan Cameron, 2022/04/29
- [PATCH v10 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Jonathan Cameron, 2022/04/29
- [PATCH v10 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port, Jonathan Cameron, 2022/04/29
- [PATCH v10 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port, Jonathan Cameron, 2022/04/29
- [PATCH v10 45/45] docs/cxl: Add switch documentation, Jonathan Cameron, 2022/04/29