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[PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL
From: |
Jonathan Cameron |
Subject: |
[PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL |
Date: |
Fri, 29 Apr 2022 15:41:06 +0100 |
Add a single complex case for aarch64 virt machine.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/qtest/cxl-test.c | 48 +++++++++++++++++++++++++++++++++--------
tests/qtest/meson.build | 1 +
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index 079011af6a..ac7d71fd74 100644
--- a/tests/qtest/cxl-test.c
+++ b/tests/qtest/cxl-test.c
@@ -17,6 +17,11 @@
"-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
"-cxl-fixed-memory-window
targets.0=cxl.0,targets.1=cxl.1,size=4G "
+#define QEMU_VIRT_2PXB_CMD "-machine virt,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
+ "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
+ "-cxl-fixed-memory-window
targets.0=cxl.0,targets.1=cxl.1,size=4G "
+
#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
/* Dual ports on first pxb */
@@ -134,18 +139,43 @@ static void cxl_2pxb_4rp_4t3d(void)
qtest_end();
}
+static void cxl_virt_2pxb_4rp_4t3d(void)
+{
+ g_autoptr(GString) cmdline = g_string_new(NULL);
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D,
+ tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs,
+ tmpfs, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+}
+
int main(int argc, char **argv)
{
+ const char *arch = qtest_get_arch();
+
g_test_init(&argc, &argv, NULL);
- qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
- qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
- qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
- qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
- qtest_add_func("/pci/cxl/rp", cxl_root_port);
- qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
- qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
- qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
- qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
+ if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
+ qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
+ qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
+ qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
+ qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
+ qtest_add_func("/pci/cxl/rp", cxl_root_port);
+ qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
+ qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
+ qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
+ qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4",
+ cxl_2pxb_4rp_4t3d);
+ } else if (strcmp(arch, "aarch64") == 0) {
+ qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4",
+ cxl_virt_2pxb_4rp_4t3d);
+ }
+
return g_test_run();
}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index dedb477890..aa78d2d537 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -215,6 +215,7 @@ qtests_aarch64 = \
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?
['tpm-tis-device-test'] : []) + \
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?
['tpm-tis-device-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test',
'fuzz-xlnx-dp-test'] : []) + \
+ qtests_cxl +
\
['arm-cpu-features',
'numa-test',
'boot-serial-test',
--
2.32.0
- [PATCH v10 31/45] CXL/cxl_component: Add cxl_get_hb_cstate(), (continued)
- [PATCH v10 31/45] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/04/29
- [PATCH v10 32/45] mem/cxl_type3: Add read and write functions for associated hostmem., Jonathan Cameron, 2022/04/29
- [PATCH v10 33/45] cxl/cxl-host: Add memops for CFMWS region., Jonathan Cameron, 2022/04/29
- [PATCH v10 34/45] hw/cxl/component Add a dumb HDM decoder handler, Jonathan Cameron, 2022/04/29
- [PATCH v10 35/45] i386/pc: Enable CXL fixed memory windows, Jonathan Cameron, 2022/04/29
- [PATCH v10 36/45] tests/acpi: q35: Allow addition of a CXL test., Jonathan Cameron, 2022/04/29
- [PATCH v10 37/45] qtests/bios-tables-test: Add a test for CXL emulation., Jonathan Cameron, 2022/04/29
- [PATCH v10 38/45] tests/acpi: Add tables for CXL emulation., Jonathan Cameron, 2022/04/29
- [PATCH v10 39/45] qtest/cxl: Add more complex test cases with CFMWs, Jonathan Cameron, 2022/04/29
- [PATCH v10 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl, Jonathan Cameron, 2022/04/29
- [PATCH v10 41/45] qtest/cxl: Add aarch64 virt test for CXL,
Jonathan Cameron <=
- [PATCH v10 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Jonathan Cameron, 2022/04/29
- [PATCH v10 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port, Jonathan Cameron, 2022/04/29
- [PATCH v10 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port, Jonathan Cameron, 2022/04/29
- [PATCH v10 45/45] docs/cxl: Add switch documentation, Jonathan Cameron, 2022/04/29