[RFC PATCH 06/40] target/arm: Remove AArch64CPUClass

[Richard Henderson]

The class structure is a plain wrapper around ARMCPUClass.  We really
only need the QOM class, TYPE_AARCH64_CPU.  The instance init and
fallback class init functions are identical to the same ones over
in cpu.c.  Make arm_cpu_post_init static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu-qom.h | 19 ++++++-------------
 target/arm/cpu.h     |  2 --
 target/arm/cpu.c     |  2 +-
 target/arm/cpu64.c   | 33 +--------------------------------
 4 files changed, 8 insertions(+), 48 deletions(-)

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 95f7805076..184b3e3726 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -26,6 +26,7 @@
 struct arm_boot_info;
 
 #define TYPE_ARM_CPU "arm-cpu"
+#define TYPE_AARCH64_CPU "aarch64-cpu"
 
 OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
 
@@ -38,13 +39,17 @@ typedef struct ARMCPUInfo {
 } ARMCPUInfo;
 
 void arm_cpu_register_parent(const ARMCPUInfo *info, const char *parent);
-void aarch64_cpu_register(const ARMCPUInfo *info);
 
 static inline void arm_cpu_register(const ARMCPUInfo *info)
 {
     arm_cpu_register_parent(info, TYPE_ARM_CPU);
 }
 
+static inline void aarch64_cpu_register(const ARMCPUInfo *info)
+{
+    arm_cpu_register_parent(info, TYPE_AARCH64_CPU);
+}
+
 /**
  * ARMCPUClass:
  * @parent_realize: The parent class' realize handler.
@@ -62,18 +67,6 @@ struct ARMCPUClass {
     ResettablePhases parent_phases;
 };
 
-
-#define TYPE_AARCH64_CPU "aarch64-cpu"
-typedef struct AArch64CPUClass AArch64CPUClass;
-DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
-                       TYPE_AARCH64_CPU)
-
-struct AArch64CPUClass {
-    /*< private >*/
-    ARMCPUClass parent_class;
-    /*< public >*/
-};
-
 void register_cp_regs_for_features(ARMCPU *cpu);
 void init_cpreg_list(ARMCPU *cpu);
 
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2b4bd20f9d..3ac650092f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1076,8 +1076,6 @@ struct ArchCPU {
 
 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
 
-void arm_cpu_post_init(Object *obj);
-
 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c97461e164..a2f59ac378 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1324,7 +1324,7 @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
 }
 
-void arm_cpu_post_init(Object *obj)
+static void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 611b233d23..1d3aff868d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1373,43 +1373,12 @@ static void aarch64_cpu_class_init(ObjectClass *oc, 
void *data)
                                           "execution state ");
 }
 
-static void aarch64_cpu_instance_init(Object *obj)
-{
-    ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
-
-    acc->info->initfn(obj);
-    arm_cpu_post_init(obj);
-}
-
-static void cpu_register_class_init(ObjectClass *oc, void *data)
-{
-    ARMCPUClass *acc = ARM_CPU_CLASS(oc);
-
-    acc->info = data;
-}
-
-void aarch64_cpu_register(const ARMCPUInfo *info)
-{
-    TypeInfo type_info = {
-        .parent = TYPE_AARCH64_CPU,
-        .instance_size = sizeof(ARMCPU),
-        .instance_init = aarch64_cpu_instance_init,
-        .class_size = sizeof(ARMCPUClass),
-        .class_init = info->class_init ?: cpu_register_class_init,
-        .class_data = (void *)info,
-    };
-
-    type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
-    type_register(&type_info);
-    g_free((void *)type_info.name);
-}
-
 static const TypeInfo aarch64_cpu_type_info = {
     .name = TYPE_AARCH64_CPU,
     .parent = TYPE_ARM_CPU,
     .instance_size = sizeof(ARMCPU),
     .abstract = true,
-    .class_size = sizeof(AArch64CPUClass),
+    .class_size = sizeof(ARMCPUClass),
     .class_init = aarch64_cpu_class_init,
 };
 
-- 
2.34.1