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[RFC PATCH 11/27] target/arm: only perform TCG cpu and machine inits if
From: |
Fabiano Rosas |
Subject: |
[RFC PATCH 11/27] target/arm: only perform TCG cpu and machine inits if TCG enabled |
Date: |
Wed, 4 Jan 2023 18:58:19 -0300 |
From: Claudio Fontana <cfontana@suse.de>
of note, cpreg lists were previously initialized by TCG first,
and then thrown away and replaced with the data coming from KVM.
Now we just initialize once, either for TCG or for KVM.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[moved arm_cpu_register_gdb_regs_for_features out of tcg_enabled]
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpu.c | 31 +++++++++++++++++-------------
target/arm/kvm.c | 18 +++++++++---------
target/arm/kvm_arm.h | 3 +--
target/arm/machine.c | 45 +++++++++++++++++++++++++-------------------
4 files changed, 54 insertions(+), 43 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f5381af437..5a132aa7bc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -524,9 +524,11 @@ static void arm_cpu_reset_hold(Object *obj)
}
#endif
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
- arm_rebuild_hflags(env);
+ if (tcg_enabled()) {
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
+ arm_rebuild_hflags(env);
+ }
}
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
@@ -1599,6 +1601,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
}
+#ifdef CONFIG_TCG
{
uint64_t scale;
@@ -1624,7 +1627,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
arm_gt_hvtimer_cb, cpu);
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
@@ -1942,17 +1946,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
unset_feature(env, ARM_FEATURE_PMU);
}
if (arm_feature(env, ARM_FEATURE_PMU)) {
- pmu_init(cpu);
-
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
+ pmu_init(cpu);
arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
- }
#ifndef CONFIG_USER_ONLY
- cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
- cpu);
+ cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
+ cpu);
#endif
+ }
} else {
cpu->isar.id_aa64dfr0 =
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
@@ -2048,11 +2051,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_VBAR);
}
- register_cp_regs_for_features(cpu);
+ if (tcg_enabled()) {
+ register_cp_regs_for_features(cpu);
+ init_cpreg_list(cpu);
+ }
+
arm_cpu_register_gdb_regs_for_features(cpu);
- init_cpreg_list(cpu);
-
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
unsigned int smp_cpus = ms->smp.cpus;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index f022c644d2..2f01c26f54 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -438,9 +438,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu,
uint64_t regidx)
return &cpu->cpreg_values[res - cpu->cpreg_indexes];
}
-/* Initialize the ARMCPU cpreg list according to the kernel's
- * definition of what CPU registers it knows about (and throw away
- * the previous TCG-created cpreg list).
+/*
+ * Initialize the ARMCPU cpreg list according to the kernel's
+ * definition of what CPU registers it knows about.
+ *
+ * The parallel for TCG is init_cpreg_list()
*/
int kvm_arm_init_cpreg_list(ARMCPU *cpu)
{
@@ -482,12 +484,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu)
arraylen++;
}
- cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
- cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
- cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
- arraylen);
- cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
- arraylen);
+ cpu->cpreg_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_values = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
+ cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
cpu->cpreg_array_len = arraylen;
cpu->cpreg_vmstate_array_len = arraylen;
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 99017b635c..41de2a7cf1 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -70,8 +70,7 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t
devid, uint64_t group,
* @cpu: ARMCPU
*
* Initialize the ARMCPU cpreg list according to the kernel's
- * definition of what CPU registers it knows about (and throw away
- * the previous TCG-created cpreg list).
+ * definition of what CPU registers it knows about.
*
* Returns: 0 if success, else < 0 error code
*/
diff --git a/target/arm/machine.c b/target/arm/machine.c
index a186787d2b..5ac1e6173a 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "internals.h"
#include "migration/cpu.h"
@@ -687,7 +688,7 @@ static int cpu_pre_save(void *opaque)
{
ARMCPU *cpu = opaque;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_start(&cpu->env);
}
@@ -722,7 +723,7 @@ static int cpu_post_save(void *opaque)
{
ARMCPU *cpu = opaque;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_finish(&cpu->env);
}
@@ -741,7 +742,7 @@ static int cpu_pre_load(void *opaque)
*/
env->irq_line_state = UINT32_MAX;
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
pmu_op_start(&cpu->env);
}
@@ -820,27 +821,28 @@ static int cpu_post_load(void *opaque, int version_id)
return -1;
}
- hw_breakpoint_update_all(cpu);
- hw_watchpoint_update_all(cpu);
+ if (tcg_enabled()) {
+ hw_breakpoint_update_all(cpu);
+ hw_watchpoint_update_all(cpu);
- /*
- * TCG gen_update_fp_context() relies on the invariant that
- * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension;
- * forbid bogus incoming data with some other value.
- */
- if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) {
- if (extract32(env->v7m.fpdscr[M_REG_NS],
- FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 ||
- extract32(env->v7m.fpdscr[M_REG_S],
- FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) {
- return -1;
+ /*
+ * TCG gen_update_fp_context() relies on the invariant that
+ * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension;
+ * forbid bogus incoming data with some other value.
+ */
+ if (arm_feature(env, ARM_FEATURE_M) &&
+ cpu_isar_feature(aa32_lob, cpu)) {
+ if (extract32(env->v7m.fpdscr[M_REG_NS],
+ FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 ||
+ extract32(env->v7m.fpdscr[M_REG_S],
+ FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) {
+ return -1;
+ }
}
- }
- if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
+ arm_rebuild_hflags(&cpu->env);
}
- arm_rebuild_hflags(&cpu->env);
return 0;
}
@@ -890,8 +892,13 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
VMSTATE_UINT32(env.exception.fsr, ARMCPU),
VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
+#ifdef CONFIG_TCG
VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
+#else
+ VMSTATE_UNUSED(sizeof(QEMUTimer *)),
+ VMSTATE_UNUSED(sizeof(QEMUTimer *)),
+#endif /* CONFIG_TCG */
{
.name = "power_state",
.version_id = 0,
--
2.35.3
- Re: [RFC PATCH 07/27] target/arm: rename handle_semihosting to tcg_handle_semihosting, (continued)
- [RFC PATCH 06/27] target/arm: cleanup cpu includes, Fabiano Rosas, 2023/01/04
- [RFC PATCH 04/27] target/arm: Remove unused includes from m_helper.c, Fabiano Rosas, 2023/01/04
- [RFC PATCH 08/27] target/arm: wrap psci call with tcg_enabled, Fabiano Rosas, 2023/01/04
- [RFC PATCH 05/27] target/arm: Remove unused includes from helper.c, Fabiano Rosas, 2023/01/04
- [RFC PATCH 09/27] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Fabiano Rosas, 2023/01/04
- [RFC PATCH 14/27] target/arm: Move regime_using_lpae_format into internal.h, Fabiano Rosas, 2023/01/04
- [RFC PATCH 15/27] target/arm: move helpers to tcg/, Fabiano Rosas, 2023/01/04
- [RFC PATCH 11/27] target/arm: only perform TCG cpu and machine inits if TCG enabled,
Fabiano Rosas <=
- [RFC PATCH 10/27] target/arm: Move PC alignment check, Fabiano Rosas, 2023/01/04
- [RFC PATCH 12/27] target/arm: Add tcg/meson.build, Fabiano Rosas, 2023/01/04
- [RFC PATCH 16/27] target/arm: only build psci for TCG, Fabiano Rosas, 2023/01/04
- [RFC PATCH 13/27] target/arm: move translate modules to tcg/, Fabiano Rosas, 2023/01/04
- [RFC PATCH 17/27] target/arm: Extract cpustate list manipulation to a file, Fabiano Rosas, 2023/01/04
- [RFC PATCH 18/27] target/arm: Move cpregs code out of cpu.h, Fabiano Rosas, 2023/01/04