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[PULL v3 18/43] target/riscv: Add some comments for sstatus CSR in riscv
From: |
Alistair Francis |
Subject: |
[PULL v3 18/43] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() |
Date: |
Fri, 6 Jan 2023 13:13:32 +1000 |
From: Bin Meng <bmeng@tinylab.org>
sstatus register dump is currently missing in riscv_cpu_dump_state().
As sstatus is a copy of mstatus, which is described in the priv spec,
it seems redundant to print the same information twice.
Add some comments for this to let people know this is intentional.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221125050354.3166023-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fe176e483..b2c132e269 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -382,6 +382,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
CSR_MHARTID,
CSR_MSTATUS,
CSR_MSTATUSH,
+ /*
+ * CSR_SSTATUS is intentionally omitted here as its value
+ * can be figured out by looking at CSR_MSTATUS
+ */
CSR_HSTATUS,
CSR_VSSTATUS,
CSR_MIP,
--
2.39.0
- [PULL v3 07/43] target/riscv: Add smstateen support, (continued)
- [PULL v3 07/43] target/riscv: Add smstateen support, Alistair Francis, 2023/01/05
- [PULL v3 09/43] target/riscv: generate virtual instruction exception, Alistair Francis, 2023/01/05
- [PULL v3 10/43] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2023/01/05
- [PULL v3 08/43] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2023/01/05
- [PULL v3 11/43] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2023/01/05
- [PULL v3 12/43] target/riscv: Enable native debug itrigger, Alistair Francis, 2023/01/05
- [PULL v3 13/43] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2023/01/05
- [PULL v3 14/43] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2023/01/05
- [PULL v3 15/43] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2023/01/05
- [PULL v3 16/43] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2023/01/05
- [PULL v3 18/43] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(),
Alistair Francis <=
- [PULL v3 17/43] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2023/01/05
- [PULL v3 22/43] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2023/01/05
- [PULL v3 19/43] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2023/01/05
- [PULL v3 21/43] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2023/01/05
- [PULL v3 20/43] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2023/01/05
- [PULL v3 23/43] target/riscv: Fix mret exception cause when no pmp rule is configured, Alistair Francis, 2023/01/05
- [PULL v3 24/43] target/riscv: Set pc_succ_insn for !rvc illegal insn, Alistair Francis, 2023/01/05
- [PULL v3 25/43] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2023/01/05
- [PULL v3 26/43] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+, Alistair Francis, 2023/01/05
- [PULL v3 27/43] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2023/01/05