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[PULL 02/46] hw/mips/malta: Trace FPGA LEDs/ASCII display updates
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 02/46] hw/mips/malta: Trace FPGA LEDs/ASCII display updates |
Date: |
Fri, 13 Jan 2023 16:44:48 +0100 |
The FPGA LEDs/ASCII display is mostly used by the bootloader
to show very low-level debug info. QEMU connects its output
to a character device backend, which is not very practical
to correlate with ASM instruction executed, interrupts or
MMIO accesses. Also, the display discard the previous states.
To ease bootloader debugging experience, add a pair of trace
events. Such events can be analyzed over time or diff-ed
between different runs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-4-philmd@linaro.org>
---
hw/mips/malta.c | 3 +++
hw/mips/trace-events | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index e9424150aa..44d88a24a7 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -58,6 +58,7 @@
#include "semihosting/semihost.h"
#include "hw/mips/cps.h"
#include "hw/qdev-clock.h"
+#include "trace.h"
#define ENVP_PADDR 0x2000
#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
@@ -120,12 +121,14 @@ static void malta_fpga_update_display_leds(MaltaFPGAState
*s)
}
leds_text[8] = '\0';
+ trace_malta_fpga_leds(leds_text);
qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
leds_text);
}
static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
{
+ trace_malta_fpga_display(s->display_text);
qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
s->display_text);
}
diff --git a/hw/mips/trace-events b/hw/mips/trace-events
index 13ee731a48..b5b882c6c2 100644
--- a/hw/mips/trace-events
+++ b/hw/mips/trace-events
@@ -4,3 +4,7 @@ gt64120_write(uint64_t addr, uint64_t value) "gt64120 write
0x%03"PRIx64" value:
gt64120_read_intreg(const char *regname, unsigned size, uint64_t value)
"gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write_intreg(const char *regname, unsigned size, uint64_t value)
"gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t
to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08"
PRIx64 "@0x%08" PRIx64
+
+# malta.c
+malta_fpga_leds(const char *text) "LEDs %s"
+malta_fpga_display(const char *text) "ASCII '%s'"
--
2.38.1
- [PULL 00/46] MIPS patches for 2023-01-13, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 01/46] hw/mips/malta: Split FPGA LEDs/ASCII display updates, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 02/46] hw/mips/malta: Trace FPGA LEDs/ASCII display updates,
Philippe Mathieu-Daudé <=
- [PULL 03/46] hw/mips/gt64xxx_pci: Accumulate address space changes, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 04/46] hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOps, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 05/46] hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.c, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 06/46] hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB hole, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 07/46] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterFields API, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 13/46] hw/mips/bootloader: Handle buffers as opaque arrays, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 09/46] hw/mips/malta: Explicit GT64120 endianness upon device creation, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 10/46] hw/mips/meson: Make gt64xxx_pci.c endian-agnostic, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 11/46] hw/mips/gt64xxx_pci: Move it to hw/pci-host/, Philippe Mathieu-Daudé, 2023/01/13
- [PULL 14/46] hw/mips/bootloader: Implement nanoMIPS NOP opcode generator, Philippe Mathieu-Daudé, 2023/01/13