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[PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test
From: |
Alistair Francis |
Subject: |
[PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test |
Date: |
Fri, 20 Jan 2023 17:38:50 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The riscv32 'spike' machine isn't bootable at this moment, requiring an
OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
QEMU rom receives the fix, we're adding a 'skip' test:
(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
SKIP: requires OpenSBI fix to work
[1]
https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 tests/avocado/riscv_opensbi.py
diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
new file mode 100644
index 0000000000..e02f0d404a
--- /dev/null
+++ b/tests/avocado/riscv_opensbi.py
@@ -0,0 +1,65 @@
+# OpenSBI boot test for RISC-V machines
+#
+# Copyright (c) 2022, Ventana Micro
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado_qemu import QemuSystemTest
+from avocado import skip
+from avocado_qemu import wait_for_console_pattern
+
+class RiscvOpenSBI(QemuSystemTest):
+ """
+ :avocado: tags=accel:tcg
+ """
+ timeout = 5
+
+ def boot_opensbi(self):
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ @skip("requires OpenSBI fix to work")
+ def test_riscv32_spike(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:spike
+ """
+ self.boot_opensbi()
+
+ def test_riscv64_spike(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:spike
+ """
+ self.boot_opensbi()
+
+ def test_riscv32_sifive_u(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:sifive_u
+ """
+ self.boot_opensbi()
+
+ def test_riscv64_sifive_u(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:sifive_u
+ """
+ self.boot_opensbi()
+
+ def test_riscv32_virt(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:virt
+ """
+ self.boot_opensbi()
+
+ def test_riscv64_virt(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:virt
+ """
+ self.boot_opensbi()
--
2.39.0
- [PULL 06/37] hw/char: riscv_htif: Remove forward declarations for non-existent variables, (continued)
- [PULL 06/37] hw/char: riscv_htif: Remove forward declarations for non-existent variables, Alistair Francis, 2023/01/20
- [PULL 10/37] hw/riscv/boot.c: introduce riscv_default_firmware_name(), Alistair Francis, 2023/01/20
- [PULL 03/37] hw/char: riscv_htif: Drop useless assignment of memory region, Alistair Francis, 2023/01/20
- [PULL 04/37] hw/char: riscv_htif: Use conventional 's' for HTIFState, Alistair Francis, 2023/01/20
- [PULL 05/37] hw/char: riscv_htif: Move registers from CPUArchState to HTIFState, Alistair Francis, 2023/01/20
- [PULL 07/37] hw/char: riscv_htif: Support console output via proxy syscall, Alistair Francis, 2023/01/20
- [PULL 08/37] hw/riscv: spike: Remove the out-of-date comments, Alistair Francis, 2023/01/20
- [PULL 11/37] hw/riscv/boot.c: Introduce riscv_find_firmware(), Alistair Francis, 2023/01/20
- [PULL 12/37] hw/riscv: spike: Decouple create_fdt() dependency to ELF loading, Alistair Francis, 2023/01/20
- [PULL 13/37] target/riscv/cpu.c: Fix elen check, Alistair Francis, 2023/01/20
- [PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test,
Alistair Francis <=
- [PULL 16/37] hw/riscv/sifive_u: use 'fdt' from MachineState, Alistair Francis, 2023/01/20
- [PULL 15/37] hw/riscv/spike: use 'fdt' from MachineState, Alistair Francis, 2023/01/20
- [PULL 17/37] hw/riscv/boot.c: exit early if filename is NULL in load functions, Alistair Francis, 2023/01/20
- [PULL 18/37] hw/riscv/spike.c: load initrd right after riscv_load_kernel(), Alistair Francis, 2023/01/20
- [PULL 19/37] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd(), Alistair Francis, 2023/01/20
- [PULL 20/37] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel(), Alistair Francis, 2023/01/20
- [PULL 21/37] hw/riscv/boot.c: use MachineState in riscv_load_initrd(), Alistair Francis, 2023/01/20
- [PULL 22/37] hw/riscv/boot.c: use MachineState in riscv_load_kernel(), Alistair Francis, 2023/01/20
- [PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props(), Alistair Francis, 2023/01/20
- [PULL 24/37] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize(), Alistair Francis, 2023/01/20