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[PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvict
From: |
Alistair Francis |
Subject: |
[PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 |
Date: |
Fri, 20 Jan 2023 17:39:09 +1000 |
From: Andrew Bresticker <abrestic@rivosinc.com>
Per the AIA specification, writes to stimecmp from VS level should
trap when hvictl.VTI is set since the write may cause vsip.STIP to
become unset.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 270de7b1a8..62e6c4acbd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1037,6 +1037,9 @@ static RISCVException write_stimecmp(CPURISCVState *env,
int csrno,
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_virt_enabled(env)) {
+ if (env->hvictl & HVICTL_VTI) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
return write_vstimecmp(env, csrno, val);
}
@@ -1057,6 +1060,9 @@ static RISCVException write_stimecmph(CPURISCVState *env,
int csrno,
RISCVCPU *cpu = env_archcpu(env);
if (riscv_cpu_virt_enabled(env)) {
+ if (env->hvictl & HVICTL_VTI) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
return write_vstimecmph(env, csrno, val);
}
--
2.39.0
- [PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props(), (continued)
- [PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props(), Alistair Francis, 2023/01/20
- [PULL 24/37] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize(), Alistair Francis, 2023/01/20
- [PULL 26/37] hw/riscv/spike.c: simplify create_fdt(), Alistair Francis, 2023/01/20
- [PULL 28/37] hw/riscv/sifive_u.c: simplify create_fdt(), Alistair Francis, 2023/01/20
- [PULL 25/37] target/riscv: Use TARGET_FMT_lx for env->mhartid, Alistair Francis, 2023/01/20
- [PULL 30/37] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id(), Alistair Francis, 2023/01/20
- [PULL 27/37] hw/riscv/virt.c: simplify create_fdt(), Alistair Francis, 2023/01/20
- [PULL 31/37] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix(), Alistair Francis, 2023/01/20
- [PULL 29/37] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus(), Alistair Francis, 2023/01/20
- [PULL 32/37] target/riscv: Fix up masking of vsip/vsie accesses, Alistair Francis, 2023/01/20
- [PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1,
Alistair Francis <=
- [PULL 34/37] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst, Alistair Francis, 2023/01/20
- [PULL 35/37] target/riscv: Introduce helper_set_rounding_mode_chkfrm, Alistair Francis, 2023/01/20
- [PULL 37/37] hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init(), Alistair Francis, 2023/01/20
- [PULL 36/37] target/riscv: Remove helper_set_rod_rounding_mode, Alistair Francis, 2023/01/20
- Re: [PULL 00/37] riscv-to-apply queue, Peter Maydell, 2023/01/21