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[PULL 01/26] target/arm: Widen cnthctl_el2 to uint64_t
From: |
Peter Maydell |
Subject: |
[PULL 01/26] target/arm: Widen cnthctl_el2 to uint64_t |
Date: |
Mon, 23 Jan 2023 13:35:28 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
This is a 64-bit register on AArch64, even if the high 44 bits
are RES0. Because this is defined as ARM_CP_STATE_BOTH, we are
asserting that the cpreg field is 64-bits.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1400
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230115171633.3171890-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bf2bce046d5..1feb63b4d73 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -479,7 +479,7 @@ typedef struct CPUArchState {
};
uint64_t c14_cntfrq; /* Counter Frequency register */
uint64_t c14_cntkctl; /* Timer Control register */
- uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
+ uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
ARMGenericTimer c14_timer[NUM_GTIMERS];
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
--
2.34.1
- [PULL 00/26] target-arm queue, Peter Maydell, 2023/01/23
- [PULL 01/26] target/arm: Widen cnthctl_el2 to uint64_t,
Peter Maydell <=
- [PULL 07/26] hw/i2c/bitbang_i2c: Convert DPRINTF() to trace events, Peter Maydell, 2023/01/23
- [PULL 09/26] hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState, Peter Maydell, 2023/01/23
- [PULL 15/26] target/arm/sme: Introduce aarch64_set_svcr(), Peter Maydell, 2023/01/23
- [PULL 11/26] hw/i2c/versatile_i2c: Use ARM_SBCON_I2C() macro, Peter Maydell, 2023/01/23
- [PULL 19/26] target/arm/sme: Unify set_pstate() SM/ZA helpers as set_svcr(), Peter Maydell, 2023/01/23
- [PULL 22/26] target/arm: Don't set EXC_RETURN.ES if Security Extension not present, Peter Maydell, 2023/01/23
- [PULL 16/26] target/arm/sme: Reset SVE state in aarch64_set_svcr(), Peter Maydell, 2023/01/23
- [PULL 21/26] target/arm: Fix in_debug path in S1_ptw_translate, Peter Maydell, 2023/01/23
- [PULL 18/26] target/arm/sme: Rebuild hflags in aarch64_set_svcr(), Peter Maydell, 2023/01/23
- [PULL 02/26] target/arm: Unify checking for M Main Extension in MRS/MSR, Peter Maydell, 2023/01/23