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Re: [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type'
From: |
Alistair Francis |
Subject: |
Re: [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type' |
Date: |
Tue, 24 Jan 2023 10:35:25 +1000 |
On Mon, Jan 23, 2023 at 7:08 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> The 'mmu-type' should reflect what the hardware is capable of so use the
> new satp_mode field in RISCVCPUConfig to do that.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/virt.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 94ff2a1584..48d034a5f7 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
> socket,
> int cpu;
> uint32_t cpu_phandle;
> MachineState *mc = MACHINE(s);
> - char *name, *cpu_name, *core_name, *intc_name;
> + uint8_t satp_mode_max;
> + char *name, *cpu_name, *core_name, *intc_name, *sv_name;
>
> for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
> cpu_phandle = (*phandle)++;
> @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,
> int socket,
> cpu_name = g_strdup_printf("/cpus/cpu@%d",
> s->soc[socket].hartid_base + cpu);
> qemu_fdt_add_subnode(mc->fdt, cpu_name);
> - if (riscv_feature(&s->soc[socket].harts[cpu].env,
> - RISCV_FEATURE_MMU)) {
> - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
> - (is_32_bit) ? "riscv,sv32" :
> "riscv,sv48");
> - } else {
> - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
> - "riscv,none");
> - }
> +
> + satp_mode_max = satp_mode_max_from_map(
> + s->soc[socket].harts[cpu].cfg.satp_mode.map);
> + sv_name = g_strdup_printf("riscv,%s",
> + satp_mode_str(satp_mode_max, is_32_bit));
> + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name);
> + g_free(sv_name);
> +
> name = riscv_isa_string(&s->soc[socket].harts[cpu]);
> qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
> g_free(name);
> --
> 2.37.2
>
>
- Re: [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool, (continued)
- [PATCH v6 3/5] riscv: Allow user to set the satp mode, Alexandre Ghiti, 2023/01/23
- [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type', Alexandre Ghiti, 2023/01/23
- [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities, Alexandre Ghiti, 2023/01/23
- Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities, Alexandre Ghiti, 2023/01/24
- Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities, Andrew Jones, 2023/01/24
Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities, Andrew Jones, 2023/01/23
Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities, Alistair Francis, 2023/01/23