[PATCH 3/5] target/tricore: Fix RRPW_DEXTR

[Bastian Koppelmann]

if we used const16 == 0 we would crash qemu with the error:

../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed

This is a special case anyways as we can directly return cpu_gpr_d[r1]
as this is the most significant word an nothing is shifted.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6149d4f5c0..62128c6aae 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8708,6 +8708,8 @@ static void decode_32Bit_opc(DisasContext *ctx)
         const16 = MASK_OP_RRPW_POS(ctx->opcode);
         if (r1 == r2) {
             tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
+        } else if (const16 == 0) {
+            tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
         } else {
             temp = tcg_temp_new();
             tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
-- 
2.39.1