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[PATCH 2/5] target/tricore: Fix OPC2_32_RCRW_INSERT translation
From: |
Bastian Koppelmann |
Subject: |
[PATCH 2/5] target/tricore: Fix OPC2_32_RCRW_INSERT translation |
Date: |
Fri, 27 Jan 2023 13:03:25 +0100 |
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8de4e56b1f..6149d4f5c0 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5805,8 +5805,8 @@ static void decode_rcrw_insert(DisasContext *ctx)
tcg_gen_movi_tl(temp, width);
tcg_gen_movi_tl(temp2, const4);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
- gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
+ tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
tcg_temp_free(temp3);
break;
--
2.39.1