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[PATCH v4 10/11] target/loongarch: Sign extend results in VA32 mode
From: |
Jiajie Chen |
Subject: |
[PATCH v4 10/11] target/loongarch: Sign extend results in VA32 mode |
Date: |
Tue, 8 Aug 2023 09:54:36 +0800 |
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 5 +++--
target/loongarch/translate.c | 13 +++++++++++++
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc
b/target/loongarch/insn_trans/trans_arith.c.inc
index e6d218e84a..39915f228d 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -72,7 +72,7 @@ static bool gen_pc(DisasContext *ctx, arg_r_i *a,
target_ulong (*func)(target_ulong, int))
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
- target_ulong addr = func(ctx->base.pc_next, a->imm);
+ target_ulong addr = va32_result(ctx, func(ctx->base.pc_next, a->imm));
tcg_gen_movi_tl(dest, addr);
gen_set_gpr(a->rd, dest, EXT_NONE);
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc
b/target/loongarch/insn_trans/trans_branch.c.inc
index 29b81a9843..41f0bfd489 100644
--- a/target/loongarch/insn_trans/trans_branch.c.inc
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -12,7 +12,7 @@ static bool trans_b(DisasContext *ctx, arg_b *a)
static bool trans_bl(DisasContext *ctx, arg_bl *a)
{
- tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ tcg_gen_movi_tl(cpu_gpr[1], va32_result(ctx, ctx->base.pc_next + 4));
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
@@ -24,7 +24,8 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
tcg_gen_addi_tl(cpu_pc, src1, a->imm);
- tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+ tcg_gen_movi_tl(dest, va32_result(ctx, ctx->base.pc_next + 4));
+
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 9cd2f13778..9703fc46a6 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -218,6 +218,19 @@ static TCGv va32_address(DisasContext *ctx, TCGv addr)
return addr;
}
+static uint64_t sign_extend32(uint64_t data)
+{
+ return (data & 0x7FFFFFFF) - (data & 0x80000000);
+}
+
+static uint64_t va32_result(DisasContext *ctx, uint64_t addr)
+{
+ if (ctx->va32) {
+ addr = sign_extend32(addr);
+ }
+ return addr;
+}
+
#include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"
--
2.41.0
- [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry, (continued)
- [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry, Jiajie Chen, 2023/08/07
- [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW, Jiajie Chen, 2023/08/07
- [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN, Jiajie Chen, 2023/08/07
- [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext, Jiajie Chen, 2023/08/07
- [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode, Jiajie Chen, 2023/08/07
- [PATCH v4 10/11] target/loongarch: Sign extend results in VA32 mode,
Jiajie Chen <=
- [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132, Jiajie Chen, 2023/08/07
- [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode, Jiajie Chen, 2023/08/07