Re: [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry

[Richard Henderson]

On 8/7/23 18:54, Jiajie Chen wrote:
> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
> zero in LoongArch32.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu-csr.h    |  9 +++++----
>   target/loongarch/tlb_helper.c | 17 ++++++++++++-----
>   2 files changed, 17 insertions(+), 9 deletions(-)

Please retain Reviewed-by when given, as I did for v3.  Anyway,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~