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[PATCH v5 01/19] target/loongarch: Support LoongArch32 TLB entry
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v5 01/19] target/loongarch: Support LoongArch32 TLB entry |
Date: |
Tue, 22 Aug 2023 09:09:54 +0200 |
From: Jiajie Chen <c@jia.je>
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn>
---
target/loongarch/cpu-csr.h | 9 +++++----
target/loongarch/tlb_helper.c | 17 ++++++++++++-----
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index f8f24032cb..48ed2e0632 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
FIELD(TLBENTRY, PLV, 2, 2)
FIELD(TLBENTRY, MAT, 4, 2)
FIELD(TLBENTRY, G, 6, 1)
-FIELD(TLBENTRY, PPN, 12, 36)
-FIELD(TLBENTRY, NR, 61, 1)
-FIELD(TLBENTRY, NX, 62, 1)
-FIELD(TLBENTRY, RPLV, 63, 1)
+FIELD(TLBENTRY_32, PPN, 8, 24)
+FIELD(TLBENTRY_64, PPN, 12, 36)
+FIELD(TLBENTRY_64, NR, 61, 1)
+FIELD(TLBENTRY_64, NX, 62, 1)
+FIELD(TLBENTRY_64, RPLV, 63, 1)
#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
FIELD(CSR_ASID, ASID, 0, 10)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 6e00190547..cef10e2257 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env,
hwaddr *physical,
tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
- tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
- tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
- tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
- tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+ if (is_la64(env)) {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+ tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+ tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+ tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+ } else {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+ tlb_nx = 0;
+ tlb_nr = 0;
+ tlb_rplv = 0;
+ }
/* Check access rights */
if (!tlb_v) {
@@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env,
hwaddr *physical,
* tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
* need adjust.
*/
- *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+ *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
(address & MAKE_64BIT_MASK(0, tlb_ps));
*prot = PAGE_READ;
if (tlb_d) {
--
2.41.0
- [PATCH v5 00/19] Based-on: https://patchew.org/QEMU/address@hidden/, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 01/19] target/loongarch: Support LoongArch32 TLB entry,
Philippe Mathieu-Daudé <=
- [PATCH v5 02/19] target/loongarch: Support LoongArch32 DMW, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 03/19] target/loongarch: Support LoongArch32 VPPN, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 05/19] target/loongarch: Extract make_address_x() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 06/19] target/loongarch: Extract make_address_i() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 07/19] target/loongarch: Extract make_address_pc() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 08/19] target/loongarch: Extract set_pc() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode, Philippe Mathieu-Daudé, 2023/08/22
- Re: [PATCH v5 00/19] Based-on: https://patchew.org/QEMU/address@hidden/, Philippe Mathieu-Daudé, 2023/08/22