[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 09/19] target/loongarch: Truncate high 32 bits of address in V
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode |
Date: |
Tue, 22 Aug 2023 09:10:02 +0200 |
From: Jiajie Chen <c@jia.je>
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
---
target/loongarch/cpu.h | 6 +++++-
target/loongarch/translate.c | 16 +++++++++++++++-
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index e1562695e8..25a0ef7e41 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -445,7 +445,11 @@ static inline bool is_va32(CPULoongArchState *env)
static inline void set_pc(CPULoongArchState *env, uint64_t value)
{
- env->pc = value;
+ if (is_va32(env)) {
+ env->pc = (uint32_t)value;
+ } else {
+ env->pc = value;
+ }
}
/*
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 8b26555a27..9a23ec786d 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -86,6 +86,10 @@ void generate_exception(DisasContext *ctx, int excp)
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
+ if (ctx->va32) {
+ dest = (uint32_t) dest;
+ }
+
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_pc, dest);
@@ -212,11 +216,17 @@ static TCGv make_address_x(DisasContext *ctx, TCGv base,
TCGv addend)
{
TCGv temp = NULL;
- if (addend) {
+ if (addend || ctx->va32) {
temp = tcg_temp_new();
+ }
+ if (addend) {
tcg_gen_add_tl(temp, base, addend);
base = temp;
}
+ if (ctx->va32) {
+ tcg_gen_ext32u_tl(temp, base);
+ base = temp;
+ }
return base;
}
@@ -262,6 +272,10 @@ static void loongarch_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
}
ctx->base.pc_next += 4;
+
+ if (ctx->va32) {
+ ctx->base.pc_next = (uint32_t)ctx->base.pc_next;
+ }
}
static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.41.0
- [PATCH v5 00/19] Based-on: https://patchew.org/QEMU/address@hidden/, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 01/19] target/loongarch: Support LoongArch32 TLB entry, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 02/19] target/loongarch: Support LoongArch32 DMW, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 03/19] target/loongarch: Support LoongArch32 VPPN, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 04/19] target/loongarch: Add LA64 & VA32 to DisasContext, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 05/19] target/loongarch: Extract make_address_x() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 06/19] target/loongarch: Extract make_address_i() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 07/19] target/loongarch: Extract make_address_pc() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 08/19] target/loongarch: Extract set_pc() helper, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH v5 09/19] target/loongarch: Truncate high 32 bits of address in VA32 mode,
Philippe Mathieu-Daudé <=
- Re: [PATCH v5 00/19] Based-on: https://patchew.org/QEMU/address@hidden/, Philippe Mathieu-Daudé, 2023/08/22