[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 05/20] target/riscv/cpu.c: add 'user_extension_properties' class
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH 05/20] target/riscv/cpu.c: add 'user_extension_properties' class prop |
Date: |
Fri, 25 Aug 2023 10:08:38 -0300 |
We want to use a post_init hook to call the cpu_instance_init callback
from each accelerator, moving repetitive code from the cpu_init()
functions to be handled by the accelerator class. But first we need to
ensure that we don't change behavior - vendor CPUs shouldn't expose user
properties, generic CPUs should expose.
Create a new 'user_extension_properties' class property. It'll be
initialized during the class init of each CPU type, where only generic
(dynamic) CPUs will enable it. This new property will be used shortly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu-qom.h | 3 +++
target/riscv/cpu.c | 46 +++++++++++++++++++++++++++++++++---------
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index f3fbe37a2c..7c76dc0dcc 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -24,6 +24,7 @@
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
+#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu"
#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
@@ -68,5 +69,7 @@ struct RISCVCPUClass {
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
+
+ bool user_extension_properties;
};
#endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 839b83e52a..e2e8724dc2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1975,6 +1975,20 @@ void riscv_cpu_list(void)
g_slist_free(list);
}
+static void riscv_dynamic_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *rcc = RISCV_CPU_CLASS(c);
+
+ rcc->user_extension_properties = true;
+}
+
+static void riscv_vendor_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *rcc = RISCV_CPU_CLASS(c);
+
+ rcc->user_extension_properties = false;
+}
+
#define DEFINE_CPU(type_name, initfn) \
{ \
.name = type_name, \
@@ -1989,6 +2003,13 @@ void riscv_cpu_list(void)
.instance_init = initfn \
}
+#define DEFINE_VENDOR_CPU(type_name, initfn) \
+ { \
+ .name = type_name, \
+ .parent = TYPE_RISCV_VENDOR_CPU, \
+ .instance_init = initfn \
+ }
+
static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU,
@@ -2003,6 +2024,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
{
.name = TYPE_RISCV_DYNAMIC_CPU,
.parent = TYPE_RISCV_CPU,
+ .class_init = riscv_dynamic_cpu_class_init,
+ .abstract = true,
+ },
+ {
+ .name = TYPE_RISCV_VENDOR_CPU,
+ .parent = TYPE_RISCV_CPU,
+ .class_init = riscv_vendor_cpu_class_init,
.abstract = true,
},
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
@@ -2012,17 +2040,17 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#endif
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34,
rv32_imafcu_nommu_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906,
rv64_thead_c906_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,
rv64_veyron_v1_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
--
2.41.0
- [PATCH 00/20] riscv: split TCG/KVM accelerators from cpu.c, Daniel Henrique Barboza, 2023/08/25
- [PATCH 01/20] target/riscv: introduce TCG AccelCPUClass, Daniel Henrique Barboza, 2023/08/25
- [PATCH 02/20] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Daniel Henrique Barboza, 2023/08/25
- [PATCH 04/20] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Daniel Henrique Barboza, 2023/08/25
- [PATCH 03/20] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Daniel Henrique Barboza, 2023/08/25
- [PATCH 05/20] target/riscv/cpu.c: add 'user_extension_properties' class prop,
Daniel Henrique Barboza <=
- [PATCH 06/20] target/riscv: add 'max_features' CPU flag, Daniel Henrique Barboza, 2023/08/25
- [PATCH 07/20] target/riscv/cpu.c: add .instance_post_init(), Daniel Henrique Barboza, 2023/08/25
- [PATCH 09/20] target/riscv/cpu.c: mark extensions arrays as 'const', Daniel Henrique Barboza, 2023/08/25
- [PATCH 08/20] target/riscv: move 'host' CPU declaration to kvm.c, Daniel Henrique Barboza, 2023/08/25
- [PATCH 10/20] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Daniel Henrique Barboza, 2023/08/25