Re: [RFC PATCH 0/3] Add API for list cpu extensions

[Daniel Henrique Barboza]

Hi Zhiwei! I have two observations:

- this API doesn't play well with KVM as is. In a KVM environment, asking for 
the
enabled extensions of the 'host' CPU returns:

$ ./mnt/qemu/bin/qemu-system-riscv64 -cpu host,help
Enable extension:
        
rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintntl_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu

This is the same set of extensions enabled in the 'rv64' CPU for TCG. This is
happening because they're sharing the same code that creates properties.

If I apply these patches on top of the "split TCG/KVM accelerators from cpu.c" I
sent earlier, this happens:

$ ./mnt/qemu/bin/qemu-system-riscv64 -cpu host,help
Enable extension:
        rv64

For TCG only CPUs (vendor CPUs) the API works even on a KVM host, regardless of
applying on top of riscv-to-apply.next or those accel patches:

$ ./mnt/qemu/bin/qemu-system-riscv64 -cpu veyron-v1,help
Enable extension:
        
rv64ch_zicbom_zicboz_zicsr_zifencei_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_xventanacondops

It seems to me that 'cpu help' doesn't engage the KVM driver accel_init() 
function.
If we decide to go ahead with this API we'll need to either figure out if 
accel-specific
initialization is possible. If not, we should declare that this API works only 
for TCG.


- I think the presence of the 'cpu help' API limits the command line parsing 
altogether,
making cheeky things like this possible:


(disabling extensions in the cmd line and asking the extensions)
$ ./build/qemu-system-riscv64 -cpu veyron-v1,icbom=false,icboz=false,help
Enable extension:
        
rv64ch_zicbom_zicboz_zicsr_zifencei_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_xventanacondops


(silly option ignored)
$ ./build/qemu-system-riscv64 -cpu veyron-v1,lalala=true,help
Enable extension:
        
rv64ch_zicbom_zicboz_zicsr_zifencei_zba_zbb_zbc_zbs_smaia_smstateen_ssaia_sscofpmf_sstc_svinval_svnapot_svpbmt_xventanacondops


This is not a gamebreaker but something to keep in mind when using this API. 
Thanks,


Daniel



On 8/25/23 09:16, LIU Zhiwei wrote:
> Some times we want to know what is the really mean of one cpu option.
> For example, in RISC-V, we usually specify a cpu in this way:
> -cpu rv64,v=on
>
> If we don't look into the source code, we can't get the ISA extensions
> of this -cpu command line.
>
> In this patch set, we add one list_cpu_props API for common cores. It
> will output the enabled ISA extensions.
>
> In the near future, I will also list all possible user configurable
> options and all possible extensions for this cpu.
>
> In order to reuse the options parse code, I also add a QemuOptsList
> for cpu.
>
>
> After this patch, we can output the extensions for cpu,
> """
>   ./qemu-system-riscv64 -cpu rv64,help
>      Enable extension:
>              
> rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
> """
>
> Notice currently this patch is only working for RISC-V system mode.
>
> Thanks Andrew Jones for your suggestion!
>
> Todo:
> 1) Output all possible user configurable options and all extensions.
> 2) Add support for RISC-V linux-user mode
> 3) Add support for other archs
>
>
> LIU Zhiwei (3):
>    cpu: Add new API cpu_type_by_name
>    target/riscv: Add API list_cpu_props
>    softmmu/vl: Add qemu_cpu_opts QemuOptsList
>
>   cpu.c                     | 39 +++++++++++++++++++++++++++------------
>   include/exec/cpu-common.h |  1 +
>   include/hw/core/cpu.h     | 11 +++++++++++
>   softmmu/vl.c              | 35 +++++++++++++++++++++++++++++++++++
>   target/riscv/cpu.c        | 10 ++++++++++
>   target/riscv/cpu.h        |  2 ++
>   6 files changed, 86 insertions(+), 12 deletions(-)