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Re: [PATCH 04/10] target/tricore: Implement FTOU insn
From: |
Bastian Koppelmann |
Subject: |
Re: [PATCH 04/10] target/tricore: Implement FTOU insn |
Date: |
Sun, 27 Aug 2023 18:36:10 +0200 |
On Sun, Aug 27, 2023 at 07:49:52AM -0700, Richard Henderson wrote:
> On 8/27/23 04:07, Bastian Koppelmann wrote:
> > On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote:
> > > On 8/26/23 09:02, Bastian Koppelmann wrote:
> > > > +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
> > > > +{
> > > > + float32 f_arg = make_float32(arg);
> > > > + uint32_t result;
> > > > + int32_t flags = 0;
> > > > +
> > > > + if (float32_is_any_nan(f_arg)) {
> > > > + result = 0;
> > > > + flags |= float_flag_invalid;
> > > > + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
> > > > + result = 0;
> > > > + flags = float_flag_invalid;
> > > > + } else {
> > > > + result = float32_to_uint32(f_arg, &env->fp_status);
> > > > + flags = f_get_excp_flags(env);
> > > > + }
> > >
> > > You should allow softfloat to diagnose the special cases, and negative -> > > > 0
> > > is standard behaviour. Therefore:
> >
> > You're right. However, there is one special case, negative -> 0 ought to
> > raise
> > float_flags_invalid.
>
> https://gitlab.com/qemu-project/qemu/-/blob/master/fpu/softfloat-parts.c.inc?ref_type=heads#L1162
Lets say the exponent is negative and the sign is negative, then we raise
float_flag_inexact and we never reach the code you mentioned here. However,
TriCore HW raises float_flag_invalid as well in that case. This is what I'm
catching with float32_lt_quiet() in the same manner as ftouz.
Cheers,
Bastian
- [PATCH 02/10] target/tricore: Implement CRCN insn, (continued)
[PATCH 05/10] target/tricore: Implement ftohp insn, Bastian Koppelmann, 2023/08/26
[PATCH 06/10] target/tricore: Implement hptof insn, Bastian Koppelmann, 2023/08/26
[PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0, Bastian Koppelmann, 2023/08/26