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[PULL 42/65] target/riscv: Allocate itrigger timers only once
From: |
Alistair Francis |
Subject: |
[PULL 42/65] target/riscv: Allocate itrigger timers only once |
Date: |
Fri, 8 Sep 2023 16:04:08 +1000 |
From: Akihiko Odaki <akihiko.odaki@daynix.com>
riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.
Divide riscv_trigger_init() into two functions, namely
riscv_trigger_realize() and riscv_trigger_reset() and call them in
appropriate timing. The timer allocation will happen only once for a
CPU in riscv_trigger_realize().
Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.h | 3 ++-
target/riscv/cpu.c | 8 +++++++-
target/riscv/debug.c | 15 ++++++++++++---
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index c471748d5a..5794aa6ee5 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -143,7 +143,8 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
-void riscv_trigger_init(CPURISCVState *env);
+void riscv_trigger_realize(CPURISCVState *env);
+void riscv_trigger_reset_hold(CPURISCVState *env);
bool riscv_itrigger_enabled(CPURISCVState *env);
void riscv_itrigger_update_priv(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bf0912014e..f227c7664e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -926,7 +926,7 @@ static void riscv_cpu_reset_hold(Object *obj)
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.debug) {
- riscv_trigger_init(env);
+ riscv_trigger_reset_hold(env);
}
if (kvm_enabled()) {
@@ -1525,6 +1525,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_cpu_register_gdb_regs_for_features(cs);
+#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.debug) {
+ riscv_trigger_realize(&cpu->env);
+ }
+#endif
+
qemu_init_vcpu(cs);
cpu_reset(cs);
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 75ee1c4971..ddd46b2d3e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -903,7 +903,17 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
CPUWatchpoint *wp)
return false;
}
-void riscv_trigger_init(CPURISCVState *env)
+void riscv_trigger_realize(CPURISCVState *env)
+{
+ int i;
+
+ for (i = 0; i < RV_MAX_TRIGGERS; i++) {
+ env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_itrigger_timer_cb, env);
+ }
+}
+
+void riscv_trigger_reset_hold(CPURISCVState *env)
{
target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
int i;
@@ -928,7 +938,6 @@ void riscv_trigger_init(CPURISCVState *env)
env->tdata3[i] = 0;
env->cpu_breakpoint[i] = NULL;
env->cpu_watchpoint[i] = NULL;
- env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- riscv_itrigger_timer_cb, env);
+ timer_del(env->itrigger_timer[i]);
}
}
--
2.41.0
- [PULL 30/65] target/riscv: check the in-kernel irqchip support, (continued)
- [PULL 30/65] target/riscv: check the in-kernel irqchip support, Alistair Francis, 2023/09/08
- [PULL 31/65] target/riscv: Create an KVM AIA irqchip, Alistair Francis, 2023/09/08
- [PULL 32/65] target/riscv: update APLIC and IMSIC to support KVM AIA, Alistair Francis, 2023/09/08
- [PULL 33/65] target/riscv: select KVM AIA in riscv virt machine, Alistair Francis, 2023/09/08
- [PULL 34/65] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/08
- [PULL 35/65] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/08
- [PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/08
- [PULL 37/65] riscv: zicond: make non-experimental, Alistair Francis, 2023/09/08
- [PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 42/65] target/riscv: Allocate itrigger timers only once,
Alistair Francis <=
- [PULL 40/65] linux-user/riscv: Add new extensions to hwprobe, Alistair Francis, 2023/09/08
- [PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I, Alistair Francis, 2023/09/08
- [PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes, Alistair Francis, 2023/09/08
- [PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec, Alistair Francis, 2023/09/08
- [PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64, Alistair Francis, 2023/09/08
- [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Alistair Francis, 2023/09/08
- [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper, Alistair Francis, 2023/09/08