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[PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64
From: |
Alistair Francis |
Subject: |
[PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64 |
Date: |
Fri, 8 Sep 2023 16:04:11 +1000 |
From: Nikita Shubin <n.shubin@yadro.com>
As per ISA:
"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."
trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4a0f6a89be..e51815c448 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3917,21 +3917,27 @@ static RISCVException riscv_csrrw_do64(CPURISCVState
*env, int csrno,
target_ulong write_mask)
{
RISCVException ret;
- target_ulong old_value;
+ target_ulong old_value = 0;
/* execute combined read/write operation if it exists */
if (csr_ops[csrno].op) {
return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
}
- /* if no accessor exists then return failure */
- if (!csr_ops[csrno].read) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- /* read old value */
- ret = csr_ops[csrno].read(env, csrno, &old_value);
- if (ret != RISCV_EXCP_NONE) {
- return ret;
+ /*
+ * ret_value == NULL means that rd=x0 and we're coming from helper_csrw()
+ * and we can't throw side effects caused by CSR reads.
+ */
+ if (ret_value) {
+ /* if no accessor exists then return failure */
+ if (!csr_ops[csrno].read) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ /* read old value */
+ ret = csr_ops[csrno].read(env, csrno, &old_value);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
}
/* write value if writable and write mask set, otherwise drop writes */
--
2.41.0
- [PULL 35/65] target/riscv: Update CSR bits name for svadu extension, (continued)
- [PULL 35/65] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/08
- [PULL 36/65] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/08
- [PULL 37/65] riscv: zicond: make non-experimental, Alistair Francis, 2023/09/08
- [PULL 38/65] hw/riscv/virt.c: fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 39/65] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/08
- [PULL 42/65] target/riscv: Allocate itrigger timers only once, Alistair Francis, 2023/09/08
- [PULL 40/65] linux-user/riscv: Add new extensions to hwprobe, Alistair Francis, 2023/09/08
- [PULL 41/65] target/riscv: Use accelerated helper for AES64KS1I, Alistair Francis, 2023/09/08
- [PULL 43/65] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes, Alistair Francis, 2023/09/08
- [PULL 44/65] target/riscv: Align the AIA model to v1.0 ratified spec, Alistair Francis, 2023/09/08
- [PULL 45/65] target/riscv: don't read CSR in riscv_csrrw_do64,
Alistair Francis <=
- [PULL 46/65] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 47/65] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Alistair Francis, 2023/09/08
- [PULL 48/65] target/riscv/cpu.c: split kvm prop handling to its own helper, Alistair Francis, 2023/09/08
- [PULL 49/65] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[], Alistair Francis, 2023/09/08
- [PULL 50/65] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 51/65] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/09/08
- [PULL 52/65] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array(), Alistair Francis, 2023/09/08