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[PULL v2 37/45] riscv: zicond: make non-experimental
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From: |
Alistair Francis |
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Subject: |
[PULL v2 37/45] riscv: zicond: make non-experimental |
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Date: |
Mon, 11 Sep 2023 16:43:12 +1000 |
From: Vineet Gupta <vineetg@rivosinc.com>
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 34ac26e3ae..bf0912014e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1869,6 +1869,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+ DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false),
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
@@ -1885,7 +1886,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
/* These are experimental so mark with 'x-' */
- DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.41.0
- [PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren, (continued)
- [PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren, Alistair Francis, 2023/09/11
- [PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext, Alistair Francis, 2023/09/11
- [PULL v2 31/45] target/riscv: Create an KVM AIA irqchip, Alistair Francis, 2023/09/11
- [PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM AIA, Alistair Francis, 2023/09/11
- [PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine, Alistair Francis, 2023/09/11
- [PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/11
- [PULL v2 30/45] target/riscv: check the in-kernel irqchip support, Alistair Francis, 2023/09/11
- [PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/11
- [PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/11
- [PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS, Alistair Francis, 2023/09/11
- [PULL v2 37/45] riscv: zicond: make non-experimental,
Alistair Francis <=
- [PULL v2 38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build, Alistair Francis, 2023/09/11
[PULL v2 39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/11
[PULL v2 40/45] linux-user/riscv: Add new extensions to hwprobe, Alistair Francis, 2023/09/11
[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I, Alistair Francis, 2023/09/11
[PULL v2 42/45] target/riscv: Allocate itrigger timers only once, Alistair Francis, 2023/09/11