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[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I
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From: |
Alistair Francis |
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Subject: |
[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I |
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Date: |
Mon, 11 Sep 2023 16:43:16 +1000 |
From: Ard Biesheuvel <ardb@kernel.org>
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230831154118.138727-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/crypto_helper.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 4d65945429..bb084e00ef 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -148,24 +148,17 @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1,
target_ulong rnum)
uint8_t enc_rnum = rnum;
uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
- uint8_t rcon_ = 0;
- target_ulong result;
+ AESState t, rc = {};
if (enc_rnum != 0xA) {
temp = ror32(temp, 8); /* Rotate right by 8 */
- rcon_ = round_consts[enc_rnum];
+ rc.w[0] = rc.w[1] = round_consts[enc_rnum];
}
- temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
- ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
- ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
- ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
+ t.w[0] = t.w[1] = t.w[2] = t.w[3] = temp;
+ aesenc_SB_SR_AK(&t, &t, &rc, false);
- temp ^= rcon_;
-
- result = ((uint64_t)temp << 32) | temp;
-
- return result;
+ return t.d[0];
}
target_ulong HELPER(aes64im)(target_ulong rs1)
--
2.41.0
- [PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS, (continued)
[PULL v2 39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build, Alistair Francis, 2023/09/11
[PULL v2 40/45] linux-user/riscv: Add new extensions to hwprobe, Alistair Francis, 2023/09/11
[PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I,
Alistair Francis <=
[PULL v2 42/45] target/riscv: Allocate itrigger timers only once, Alistair Francis, 2023/09/11
[PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes, Alistair Francis, 2023/09/11
[PULL v2 44/45] target/riscv: Align the AIA model to v1.0 ratified spec, Alistair Francis, 2023/09/11
[PULL v2 45/45] target/riscv: don't read CSR in riscv_csrrw_do64, Alistair Francis, 2023/09/11
Re: [PULL v2 00/45] riscv-to-apply queue, Stefan Hajnoczi, 2023/09/11
Re: [PULL v2 00/45] riscv-to-apply queue, Michael Tokarev, 2023/09/12