Expected UART interrupt behavior on mps2_an521

[Eskowitz, Michael]

Hello,

I hope this is a simple question.  I have been unable to find documentation related to interrupt behavior on the UART of the mps2_an521.  Application note AN521 does not go into great depth in this area and I am hoping that someone can either address my question or point me in the right direction.  Thank you in advance for your help.

I have encountered what is possibly an emulation issue in Qemu related to the receive interrupt of the UART.  If I disable the receive interrupt for the UART and a character arrives such that the UART’s one byte buffer becomes full while the receive interrupt is disabled, should an interrupt fire when I re-enable the receive interrupt provided that the buffer is still full?

The implementation in Qemu does not fire an interrupt when the receive interrupt is re-enabled and since the buffer is full, no further characters are placed in the buffer to trigger further interrupts.  The receive chain on my interrupt driven application is thus broken in simulation depending upon the timing of characters arriving at the interface.  I am uncertain if this is an emulation issue or an issue with my application.  Unfortunately, I do not currently have the physical hardware to test this scenario to see the proper behavior. 

Any insight that you can provide would be greatly appreciated.  Thank you so much.

-Mike