Re: Expected UART interrupt behavior on mps2_an521

[Peter Maydell]

On Thu, 5 Jan 2023 at 22:47, Eskowitz, Michael
<Michael.Eskowitz@analog.com> wrote:
> I hope this is a simple question.  I have been unable to find
> documentation related to interrupt behavior on the UART of the
> mps2_an521.  Application note AN521 does not go into great depth
> in this area and I am hoping that someone can either address my
> question or point me in the right direction.

> I have encountered what is possibly an emulation issue in Qemu
> related to the receive interrupt of the UART.  If I disable the
> receive interrupt for the UART and a character arrives such that
> the UART’s one byte buffer becomes full while the receive interrupt
> is disabled, should an interrupt fire when I re-enable the receive
> interrupt provided that the buffer is still full?

The UART in the MPS2 boards is the CMSDK APB UART, which is
documented in the  Cortex-M System Design Kit Technical Reference
Manual (ARM DDI0479):
https://developer.arm.com/documentation/ddi0479/
Unfortunately it's not very detailed. It's possible we've implemented
something that's not exactly what the hardware does, but you'd need to
cross-check against the hardware behaviour to confirm that.

thanks
-- PMM