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Re: [Qemu-ppc] Regression in ppc-softmmu when running HelenOS

From: Alexander Graf
Subject: Re: [Qemu-ppc] Regression in ppc-softmmu when running HelenOS
Date: Wed, 14 Mar 2012 03:49:35 +0100

On 14.03.2012, at 03:46, Mark Cave-Ayland wrote:

> On 14/03/12 02:22, Alexander Graf wrote:
>>> 2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are
>>> loaded with information specific to the interrupt
>>> type.
>>> - These bits are not relevant on PPC32 since MSR is only 32-bit.
>> PowerPC begins counting with the most significant bit, so they are in the 
>> 32-bit range.
> But I thought that the QEMU order was the reverse as given in the 
> specification? For example, on p.735 describing the MSR, the SF (Sixty Four) 
> bit flag is described as bit 0, where as in target-ppc/cpu.h MSR_SF is given 
> as 63.

Yes, exactly :). So if the spec says that bits 33-36 and 42-47 are loaded with 
interrupt specific information, these fall into the lower 32 bits.
In QEMU, we use the typical C notion where the LSB is 0. That makes it 
confusing to understand what's going on at times, as all the numbers diverge 
from the spec. But that's life.


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