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Re: [Qemu-ppc] [Qemu-devel] [PATCH 2/2] PPC: Fix TLB invalidation bug wi

From: Andreas Färber
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 2/2] PPC: Fix TLB invalidation bug within the PPC interrupt handler.
Date: Wed, 28 Mar 2012 18:47:21 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120312 Thunderbird/11.0

Am 28.03.2012 02:45, schrieb David Gibson:
> On Tue, Mar 27, 2012 at 04:41:55PM +0100, Mark Cave-Ayland wrote:
>> Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB
>> flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR
>> bits at the start of the interrupt handler, the logic towards the end of the
>> handler to force a TLB flush if either one of these bits were set would never
>> be triggered.
>> This patch simply changes the IR/DR bit check in the TLB flush logic to use
>> the original MSR value (albeit with some interrupt-specific bits cleared) so
>> that the IR/DR bits are preserved at the point where the check takes place.
>> Signed-off-by: Mark Cave-Ayland <address@hidden>
> Acked-by: David Gibson <address@hidden>

Thanks, compile-tested and applied to ppc-next:


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