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Re: [Qemu-ppc] [Qemu-devel] [PATCH 1/2] PPC: Fix interrupt MSR value wit

From: Scott Wood
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler.
Date: Thu, 29 Mar 2012 14:06:49 -0500
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111115 Thunderbird/8.0

On 03/29/2012 04:11 AM, Mark Cave-Ayland wrote:
>>> What about POWERPC_EXCP_40x?  And are all the classic chips OK with the
>>> 2.06B implementation?
>> Hrm, yeah.  I think what you ought to do is to use the new logic just
>> for the "classic" exception models.  Have the default branch remain
>> the one that just masks ME.  That's wrong, but it's the same wrong as
>> we have already, and we can fix it later once we've verified what the
>> right thing to do is for 40x and BookE.
> I'm actually coming at this from a fixing what was potentially an
> OpenBIOS bug rather than a PPC angle, so I have to admit I have no I
> idea which ones are the "classic" exception models. Would you consider
> this to be just EXCP_STD, EXCP_6* and EXCP_7*?

Also POWERPC_EXCP_G2, and maybe POWERPC_EXCP_970?  Even on server
there's a question of whether it's a 2.06 chip or previous version of
the architecture.

One thing that sticks out for classic chips that is missing here is
MSR[POW], which should be cleared on exceptions.


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