[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] Qemu pSeries AIX ADB boot

From: Alexander Graf
Subject: Re: [Qemu-ppc] Qemu pSeries AIX ADB boot
Date: Tue, 12 Jun 2012 10:45:28 +0200
User-agent: Thunderbird (X11/20090817)

Michael Sabino wrote:
> I'm not sure why when I type "info registers" a register called NIP is
> cycling through several different values and reaching the same point
> at times. some other registers also seem to be changing.

That's perfectly fine. It means the guest checks something in a loop -
maybe some hardware button, maybe it's checking on the exact condition
it's failing on. Who knows :).

> IN:
> 0x000000000095e7a4:  cmpwi   r3,0
> 0x000000000095e7a8:  beq+    0x95e7a0
> IN:
> 0x000000000095e7a0:  bl      0x1e5be0
> That is the last thing I see in the instruction log after putting in
> some generic spr's and applying the PPP code below.
> I don't get any more invalid spr's after I edited translate_init.c.
> Here is some sPAPR pSeries Partition Pool code that I think is better
> than the version in the aix qemu tree. It seems to compile, but it
> does not get me any further as far as I can tell.
> It's based on the suggestion of Alex to look at
> http://lxr.free-electrons.com/source/arch/powerpc/kernel/lparcfg.c?a=m68k#L108.
> static target_ulong h_get_ppp(CPUPPCState *env, sPAPREnvironment *spapr,
>                               target_ulong opcode, target_ulong *args)
> {
>     printf("\nh_get_ppp might not be right yet\n");
>     env->gpr[4] = 100; // Processor capacity percentage
>     env->gpr[5] = 0; // Unallocated processor capacity percentage

This won't work. args is synchronized back onto the GPRs.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]