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Re: [Qemu-riscv] [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the
From: |
Alistair Francis |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code |
Date: |
Tue, 20 Nov 2018 15:22:09 -0800 |
On Mon, Nov 19, 2018 at 10:55 PM Richard Henderson
<address@hidden> wrote:
>
> On 11/20/18 12:04 AM, Alistair Francis wrote:
> > On Fri, Nov 16, 2018 at 9:26 AM Richard Henderson
> > <address@hidden> wrote:
> >>
> >> On 11/15/18 11:36 PM, Alistair Francis wrote:
> >>> + tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
> >>> + tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
> >>> + tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
> >>
> >> Why are these three reserved?
> >
> > Do these not need to be? I thought we had to reserve them.
>
> The return address, I presume, has been saved by the prologue. I see no
> reason
> why it can't be yet another call-clobbered register.
Ok, removed.
>
> As for the other two... what are they supposed to be?
They were old temp registers. L1 wasn't even used and I have replace
L0 with TMP0 as we have enough tmp registers.
Alistair
>
>
> r~
- Re: [Qemu-riscv] [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions, (continued)
[Qemu-riscv] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/11/15
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support, no-reply, 2018/11/16