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[Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to R
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array |
Date: |
Wed, 18 Sep 2019 07:56:21 -0700 |
From: Bin Meng <address@hidden>
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/riscv_hart.c | 3 ++-
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 6620e41cb7..5b98227db6 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -29,6 +29,7 @@
static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+ DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
DEFINE_PROP_END_OF_LIST(),
};
@@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int
idx,
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
sizeof(RISCVCPU), cpu_type,
&error_abort, NULL);
- s->harts[idx].env.mhartid = idx;
+ s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
object_property_set_bool(OBJECT(&s->harts[idx]), true,
"realized", &err);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 3b52b50571..c75856fa73 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState {
/*< public >*/
uint32_t num_harts;
+ uint32_t hartid_base;
char *cpu_type;
RISCVCPU *harts;
} RISCVHartArrayState;
--
2.21.0
- [Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, (continued)
- [Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 18/48] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18