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[Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nod
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes |
Date: |
Wed, 18 Sep 2019 07:56:26 -0700 |
From: Bin Meng <address@hidden>
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d80b203cc1..7eefe9796a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -79,6 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
char ethclk_names[] = "pclk\0hclk\0tx_clk";
uint32_t plic_phandle, ethclk_phandle, phandle = 1;
uint32_t uartclk_phandle;
+ uint32_t hfclk_phandle, rtcclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
@@ -97,6 +98,28 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+ hfclk_phandle = phandle++;
+ nodename = g_strdup_printf("/hfclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_HFCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
+ rtcclk_phandle = phandle++;
+ nodename = g_strdup_printf("/rtcclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_RTCCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/memory@%lx",
(long)memmap[SIFIVE_U_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 6b2b5b68e2..24418145aa 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -69,6 +69,8 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
+ SIFIVE_U_HFCLK_FREQ = 33333333,
+ SIFIVE_U_RTCCLK_FREQ = 1000000,
SIFIVE_U_GEM_CLOCK_FREQ = 125000000
};
--
2.21.0
- [Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, (continued)
- [Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/18