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[RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions
From: |
frank . chang |
Subject: |
[RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions |
Date: |
Wed, 22 Jul 2020 17:16:01 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 6b4b7f6574..af19561e7d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3384,11 +3384,11 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr
*a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen;
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
@@ -3415,7 +3415,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr
*a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen) {
+ int vlmax = s->vlen * s->flmul / (1 << (s->sew + 3));
+ if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
--
2.17.1
- [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction, (continued)
- [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/22
- [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/22
- [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/22
- [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/22
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, frank . chang, 2020/07/22
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions,
frank . chang <=
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/22
- [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/22