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Re: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions


From: Frank Chang
Subject: Re: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions
Date: Fri, 31 Jul 2020 18:17:48 +0800

On Fri, Jul 31, 2020 at 4:35 AM Richard Henderson <richard.henderson@linaro.org> wrote:
On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> +    static gen_helper_gvec_3_ptr * const fns[6][4] = {
> +        {
> +            NULL, gen_helper_vzext_vf2_h,
> +            gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d
> +        },
> +        {
> +            NULL, NULL,
> +            gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d,
> +        },
> +        {
> +            NULL, NULL,
> +            NULL, gen_helper_vzext_vf8_d
> +        },
> +        {
> +            NULL, gen_helper_vsext_vf2_h,
> +            gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d
> +        },
> +        {
> +            NULL, NULL,
> +            gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d,
> +        },
> +        {
> +            NULL, NULL,
> +            NULL, gen_helper_vsext_vf8_d
> +        }
> +    };

I don't understand why there aren't more functions in this table.  As far as I
can see, the only NULLs should be at [*][0].


r~

As source EEW has to be 1/2, 1/4, 1/8 of SEW and the source EEW must be
a supported width (Section 12.3).

Shouldn't it impossible to have the cases, e.g.
vzext.vf4 with SEW = 16, i.e. EEW = SEW / 4 = 4 bits
vzext.vf8 with SEW = 16, i.e. EEW = SEW / 8 = 2 bits
vzext.vf8 with SEW = 32, i.e. EEW = SEW / 8 = 4 bits

Frank Chang

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