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[RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction
From: |
frank . chang |
Subject: |
[RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction |
Date: |
Wed, 30 Sep 2020 03:04:03 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 7 ++++---
target/riscv/vector_helper.c | 6 +++---
4 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 50cca2952c..e046591a42 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1070,7 +1070,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 958914458d..0cb76682a0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -602,7 +602,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
-vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
+vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 1cd0f9b8d1..f9d280b0c5 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2911,8 +2911,8 @@ GEN_MM_TRANS(vmnor_mm)
GEN_MM_TRANS(vmornot_mm)
GEN_MM_TRANS(vmxnor_mm)
-/* Vector mask population count vmpopc */
-static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
+/* Vector mask population count vpopc */
+static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s)) {
@@ -2931,13 +2931,14 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
+ gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc);
gen_set_gpr(a->rd, dst);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free(dst);
tcg_temp_free_i32(desc);
+
return true;
}
return false;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8556ab3b0d..517e7344b9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4420,9 +4420,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
-/* Vector mask population count vmpopc */
-target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* Vector mask population count vpopc */
+target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
target_ulong cnt = 0;
uint32_t vm = vext_vm(desc);
--
2.17.1
- [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions, (continued)
- [RFC v5 18/68] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/09/29
- [RFC v5 19/68] target/riscv: rvv-1.0: index load and store instructions, frank . chang, 2020/09/29
- [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/09/29
- [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/09/29
- [RFC v5 22/68] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/09/29
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/09/29
- [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/09/29
- [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/09/29
- [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/09/29
- [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/09/29
- [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction,
frank . chang <=
- [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/09/29
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/09/29
- [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/09/29
- [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/09/29
- [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/09/29
- [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/09/29
- [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/09/29
- [RFC v5 37/68] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 38/68] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/09/29