[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions
From: |
frank . chang |
Subject: |
[RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions |
Date: |
Wed, 30 Sep 2020 03:04:05 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++-
target/riscv/vector_helper.c | 4 ----
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d7dac12883..0fed7c9e56 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -604,9 +604,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
-vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
-vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
-vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
+vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
+vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
+vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index c34877140f..ae2b224b0f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2982,7 +2982,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s) && \
+ require_vm(a->vm, a->rd) && \
+ (a->rd != a->rs2)) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ecc9be7733..8ccf538141 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4466,7 +4466,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
@@ -4496,9 +4495,6 @@ static void vmsetm(void *vd, void *v0, void *vs2,
CPURISCVState *env,
}
}
}
- for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, i, 0);
- }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
--
2.17.1
- [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, (continued)
- [RFC v5 20/68] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/09/29
- [RFC v5 21/68] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2020/09/29
- [RFC v5 22/68] target/riscv: rvv-1.0: amo operations, frank . chang, 2020/09/29
- [RFC v5 23/68] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2020/09/29
- [RFC v5 24/68] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/09/29
- [RFC v5 25/68] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/09/29
- [RFC v5 26/68] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/09/29
- [RFC v5 27/68] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/09/29
- [RFC v5 28/68] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/09/29
- [RFC v5 29/68] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/09/29
- [RFC v5 30/68] target/riscv: rvv-1.0: set-X-first mask bit instructions,
frank . chang <=
- [RFC v5 31/68] target/riscv: rvv-1.0: iota instruction, frank . chang, 2020/09/29
- [RFC v5 32/68] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/09/29
- [RFC v5 33/68] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/09/29
- [RFC v5 34/68] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/09/29
- [RFC v5 35/68] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 36/68] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/09/29
- [RFC v5 37/68] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/09/29
- [RFC v5 38/68] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/09/29
- [RFC v5 39/68] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/09/29
- [RFC v5 41/68] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/09/29