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[RFC v2 03/15] target/riscv: rvb: count bits set
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From: |
frank . chang |
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Subject: |
[RFC v2 03/15] target/riscv: rvb: count bits set |
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Date: |
Wed, 16 Dec 2020 10:01:28 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32-64.decode | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
target/riscv/translate.c | 6 ++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index f4c42720fc7..00c56a93151 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+pcntw 0110000 00010 ..... 001 ..... 0011011 @r2
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8fe838cf0d0..ac4d8395a45 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
# *** RV32B Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
+pcnt 011000 000010 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index fb6e16143db..f5930f2ad53 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
return gen_unary(ctx, a, &gen_ctz);
}
+static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
@@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
return gen_unary(ctx, a, &gen_ctzw);
}
+static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, &gen_pcntw);
+}
+
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 398d4502a96..4c9eb86e630 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -726,6 +726,12 @@ static void gen_clzw(TCGv ret, TCGv arg1)
tcg_gen_subi_i64(ret, ret, 32);
}
+static void gen_pcntw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ext32u_tl(arg1, arg1);
+ tcg_gen_ctpop_tl(ret, arg1);
+}
+
#endif
static bool gen_arith(DisasContext *ctx, arg_r *a,
--
2.17.1
- [RFC v2 00/15] support subsets of bitmanip extension, frank . chang, 2020/12/15
- [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2020/12/15
- [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2020/12/15
- [RFC v2 03/15] target/riscv: rvb: count bits set,
frank . chang <=
- [RFC v2 04/15] target/riscv: rvb: logic-with-negate, frank . chang, 2020/12/15
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/12/15
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15