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Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instruction

From: LIU Zhiwei
Subject: Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions
Date: Thu, 12 Aug 2021 13:03:07 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 2021/8/12 下午12:42, Richard Henderson wrote:
On 8/11/21 12:40 PM, LIU Zhiwei wrote:
If the software doesn't use the high part, who cares the really value in high part? Do you know the benefit?  Thanks again.

I do not.

I simply presume that they already have the hardware, in the form of the addw instruction, etc.

The mistake, I think, was changing the definition of "add" in the first place, which required the addition of a different opcode "addw", which is then undefined for RV32.

Sorry, I don't get "the mistake" here. Do you think the specification is not right.
Or the QEMU implementation of this patch set is not right?
Currently I don't know there is  a 64-bit hardware which has done with UXL32.

They should simply have had "addw" and "addq" as different opcodes that didn't change behaviour.  Etc.

I don't get  this statement. Is it related to UXL32?

Best Regards,

But what's done is done.


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