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Re: [PATCH] tcg/riscv: Fix potential bug in clobbered call register set

From: Richard Henderson
Subject: Re: [PATCH] tcg/riscv: Fix potential bug in clobbered call register set
Date: Mon, 27 Sep 2021 09:10:57 -0400
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/27/21 1:36 AM, Philippe Mathieu-Daudé wrote:
There are not 64 registers, so this is incorrect.

Currently there are 32 registers, but I was looking at this draft:
"The vector extension adds 32 architectural vector registers, v0-v31
to the base scalar RISC-V ISA."
If this were to be implemented (and available on the host), wouldn't
we have 64 registers?

Sure. But there are *lots* of changes required before that happens, and certainly you shouldn't be assuming what the ABI is now.

Eventually this line would be easier to review as:

   tcg_target_call_clobber_regs = MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS);

Would it?  Or would it be eaier to review with

  tcg_target_call_clobber_regs = 0;

followed by a set of each register that is call clobbered.

Why are you assuming that it's safer to list unknown registers as call-clobbered? IF ANYTHING, it might be safer to assume that all new registers are caller saved.

But as a general principal, I also don't like register masks containing set bits outside the range of the mask.


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