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Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritm

From: Richard Henderson
Subject: Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers
Date: Wed, 20 Oct 2021 07:14:07 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
Introduction of a gen_logic function for bitwise logic to implement
instructions in which not propagation of information occurs between bits and
use of this function on the bitwise instructions.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
  target/riscv/translate.c                | 27 +++++++++++++++++++++++++
  target/riscv/insn_trans/trans_rvb.c.inc |  6 +++---
  target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------
  3 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 121fcd71fe..3c2e9fb790 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -382,6 +382,33 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
  /* Include the auto-generated decoder for 32 bit insn */
  #include "decode-insn32.c.inc"
+static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
+                             void (*func)(TCGv, TCGv, target_long))
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    func(dest, src1, a->imm);
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                      void (*func)(TCGv, TCGv, TCGv))

I think you should drop the ext argument, which is (by nature of the operations) universally EXT_NONE for all callers. Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


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